公开(公告)号：US06404056B1

公开(公告)日：2002-06-11

申请号：US09313249

申请日：1999-05-18

Applicant: Shigehiro Kuge ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

Inventor： Shigehiro Kuge ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC: H01L2940

CPC classification number: H01L23/5286 ,  H01L27/0207 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: On transistors P1, P2, N1 and N2 constituting an NAND gate, a interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the interconnection pattern W of metal having high melting point, signal lines SL and SL′ for signal input/output between the NAND gate and the outside are formed by aluminum interconnection pattern Al1, and power supply lines VL and VL′ for applying power supply potentials Vcc and Vss to the NAND gate are formed by the aluminum interconnection pattern Al2. As compared with the prior art in which the local line LL is formed by the aluminum interconnection pattern Al1, the degree of freedom in layout can be improved and the layout area can be reduced.

Abstract translation: 在构成NAND门的晶体管P1，P2，N1，N2上，堆叠具有高熔点金属的互连图案W和铝互连图案Al1和Al2。 用于将晶体管P1，P2，N1和N2相互连接的本地线路LL通过具有高熔点金属的互连图案W，在与非门与外部之间的信号输入/输出的信号线SL和SL'形成 由铝互连图案Al1形成，并且用于将电源电位Vcc和Vss施加到NAND门的电源线VL和VL'由铝互连图案Al2形成。 与通过铝互连图案Al1形成局部线LL的现有技术相比，可以提高布局的自由度，并且可以减小布局面积。

公开(公告)号：US6069379A

公开(公告)日：2000-05-30

申请号：US968897

申请日：1997-11-06

Applicant: Hiroshi Kimura ,  Tadashi Nishimura ,  Takahiro Tsuruda ,  Kazutami Arimoto ,  Tadato Yamagata ,  Kazuyasu Fujishima

Inventor： Hiroshi Kimura ,  Tadashi Nishimura ,  Takahiro Tsuruda ,  Kazutami Arimoto ,  Tadato Yamagata ,  Kazuyasu Fujishima

IPC: H01L21/335 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10852

Abstract: In a semiconductor device and a method of manufacturing the same, an isolating and insulating film is provided at an end neighboring to a second impurity region with a groove extended to a semiconductor substrate. This removes a crystal defect existed at the end of the isolating and insulating film, and thus prevents leak of a current at this portion from a storage node. Consequently, provision of the groove at the edge portion of the isolating oxide film neighboring to the impurity region removes a crystal defect at this region, and thus eliminates a possibility of leak of a current.

Abstract translation: 在半导体器件及其制造方法中，隔离绝缘膜设置在与第二杂质区相邻的端部处，并且沟槽延伸到半导体衬底。 这消除了隔离和绝缘膜末端存在的晶体缺陷，从而防止在该部分处的电流从存储节点泄漏。 因此，在与杂质区相邻的隔离氧化膜的边缘部分处设置沟槽消除了该区域的晶体缺陷，从而消除了电流泄漏的可能性。

公开(公告)号：US5894440A

公开(公告)日：1999-04-13

申请号：US189276

申请日：1994-01-31

Applicant: Masaki Tsukude ,  Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi

Inventor： Masaki Tsukude ,  Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi

IPC: G11C11/401 ,  G11C7/06 ,  G11C7/10 ,  G11C11/409

CPC classification number: G11C7/06 ,  G11C7/1006 ,  G11C7/1039

Abstract: Each of divided bit line pairs is selectively connected to a sub-input/output line pair through transfer gates. A register is connected to the sub-input/output line pair. Data is transferred through the sub-input/output line pair between the register and a selected bit line pair. A sense amplifier is connected to each of the bit line pairs. Sense amplifiers are independently driven by separate sense amplifier activating signals. Therefore, even if data is transferred to the selected bit line pair from the register, fluctuations in potential on the bit line pair caused in such a case does not affect a sense amplifier activating signal connected to a non-selected bit line pair. As a result, data stored in the non-selected memory cell is prevented from being destroyed.

Abstract translation: 每个分开的位线对通过传输门选择性地连接到子输入/输出线对。 寄存器连接到子输入/输出线对。 数据通过寄存器和所选位线对之间的子输入/输出线对传输。 读出放大器连接到每个位线对。 感测放大器由独立的读出放大器激活信号驱动。 因此，即使数据从寄存器传送到所选择的位线对，在这种情况下引起的位线对上的电位波动也不影响连接到未选位线对的读出放大器激活信号。 结果，防止存储在未选择的存储单元中的数据被破坏。

公开(公告)号：USRE36027E

公开(公告)日：1999-01-05

申请号：US664081

申请日：1996-06-13

Applicant: Kazutami Arimoto ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Masaki Tsukude ,  Tsukasa Ohishi

Inventor： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Masaki Tsukude ,  Tsukasa Ohishi

IPC: G11C11/409 ,  G11C7/10 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/41 ,  H01L27/10 ,  G11C7/00

CPC classification number: G11C7/12 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/1048

Abstract: In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of V.sub.CC -V.sub.th, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of 1/2.multidot.V.sub.CC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.

Abstract translation: 在CSL系统的动态RAM中，存储器阵列被分成多个存储器阵列部分，并且设置在各个存储器阵列部分中的位线对响应于CSL输出而同时连接到它们对应的I / O线对 。 在这样的RAM中，只有要访问的存储器阵列部分的I / O线对被预充电到VCC-Vth的电平，而不存储阵列部分的I / O线对被预充电到 + E，fra 1/2 + EE xVCC的电平与位线对相同。 这使得可以实现更快的数据读取操作，并且还防止不必要的电流在未加工的存储器阵列部分中的位线对和I / O线对之间流动。

公开(公告)号：US5588130A

公开(公告)日：1996-12-24

申请号：US283367

申请日：1994-08-01

Applicant: Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

Inventor： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

IPC: G06F12/08 ,  G11C7/10 ,  G06F13/00 ,  G11C15/00

CPC classification number: G06F12/0893 ,  G11C7/1021

Abstract: A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

公开(公告)号：US5371714A

公开(公告)日：1994-12-06

申请号：US26225

申请日：1993-02-26

Applicant: Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka

Inventor： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka

IPC: G11C7/10 ,  G11C8/14 ,  G11C8/18 ,  G11C8/00

CPC classification number: G11C8/14 ,  G11C7/1036 ,  G11C7/1039 ,  G11C8/18 ,  H01L2924/01074

Abstract: In a block access memory in which the memory cell array is divided into a plurality of blocks and data input/output is carried out by block unit, each block is divided into a plurality of subblocks, and the timing of activating the word line and the timing of activating the sense amplifier are made different for each subblock in the block in which the selected word line is included, whereby the peak current associated with the bit line charge/discharge at the time of activating the sense amplifiers is reduced.

Abstract translation: 在其中存储单元阵列被划分成多个块并且通过块单元执行数据输入/输出的块存取存储器中，每个块被划分成多个子块，并且激活字线和 激活读出放大器的定时对于其中包括所选择的字线的块中的每个子块而言是不同的，从而降低与激活读出放大器时的位线充电/放电相关联的峰值电流。

公开(公告)号：US5267214A

公开(公告)日：1993-11-30

申请号：US616264

申请日：1990-11-20

Applicant: Kazuyasu Fujishima ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude

Inventor： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude

IPC: G11C11/409 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/34

CPC classification number: G11C11/4091 ,  G11C11/4076

Abstract: A dynamic random access memory amplifier arrangement includes a sense amplifier band shared between two different memory blocks. In this memory, only sense amplifiers related to a selected memory block are activated. The memory comprises a circuit for boosting a control signal voltage to a switching unit for connecting the selected memory block to the sense amplifiers up to a level higher than a power supply voltage Vcc during the activation of the sense amplifiers, and a circuit for separating a memory block paired with the selected memory block from the activated sense amplifiers during the sensing operation. The memory further comprises a circuit for generating a control signal of the power supply voltage Vcc and connecting all the memory blocks to the corresponding sense amplifiers in a stand-by state wherein a row address strobe signal is inactive. With this arrangement, a highly reliable memory consuming less power can be achieved which ensures data writing and/or rewriting at a full Vcc level.

Abstract translation: 动态随机存取存储器放大器装置包括在两个不同存储块之间共享的读出放大器带。 在该存储器中，只有与所选存储器块相关的读出放大器被激活。 存储器包括用于将控制信号电压升压到开关单元的电路，用于在感测放大器的激活期间将选择的存储块连接到读出放大器，直到高于电源电压Vcc的电平，以及用于分离 存储块在感测操作期间与所激活的读出放大器与选择的存储块配对。 存储器还包括用于产生电源电压Vcc的控制信号的电路，并且在行地址选通信号无效的待机状态下将所有存储块连接到相应的读出放大器。 通过这种布置，可以实现消耗更少功率的高度可靠的存储器，其确保在完全Vcc级别的数据写入和/或重写。

公开(公告)号：US5189316A

公开(公告)日：1993-02-23

申请号：US706925

申请日：1991-05-31

Applicant: Shuji Murakami ,  Kazuyasu Fujishima

Inventor： Shuji Murakami ,  Kazuyasu Fujishima

IPC: G11C11/417 ,  G05F1/46 ,  G05F3/24 ,  G11C5/14 ,  G11C11/407

CPC classification number: G05F1/465 ,  G05F3/24 ,  G11C5/147

Abstract: In an active mode, a transistor 61 or 63 is turned on, so that a reference voltage generator circuit 1 and an internal voltage correcting circuit 2 are activated. Consequently, an internal voltage V.sub.INT which is stepped down is applied to an internal main circuit 7. Conversely, in a standby mode, a transistor 61 or 63 is turned off, so that the reference voltage generator circuit 1 and the internal voltage correcting circuit 2 are inactivated. Consequently, the current does not flow in the reference voltage generator circuit 1 and the internal voltage correcting circuit 2, resulting in reduction of a consumption power. Simultaneously, a transistor 62 or 64 is turned on, so that a source voltage Ext.Vcc is directly applied to the internal main circuit 7 through the transistor 62 or 23. Thereby, operation conditions of logic circuits in the internal main circuit 7 are maintained.

公开(公告)号：US5103426A

公开(公告)日：1992-04-07

申请号：US528511

申请日：1990-05-25

Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC: H01L21/82 ,  G11C5/06 ,  G11C8/00 ,  G11C8/12 ,  G11C11/401 ,  G11C29/00 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H03M7/00 ,  H03M7/22

CPC classification number: G11C8/12 ,  G11C5/066 ,  G11C29/006

Abstract: An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when a selecting signal is applied to the first stage branch portion. The second stage output portion, to which the selecting signal is applied, outputs a selecting signal on one of two output portions in response to the second bit information of the address signal, in accordance with the selecting signal. Thereafter, each branch portion of the third to last stages outputs a selecting signal on one of two output portions in response to respective contents of the third bit to last bit of the address signal in accordance with the selecting signal applied from the preceding stage. By this selecting signal, a memory cell as a functional block portion is selected and is activated.

公开(公告)号：US5077688A

公开(公告)日：1991-12-31

申请号：US591635

申请日：1990-10-02

Applicant: Masaki Kumanoya ,  Kazuyasu Fujishima

Inventor： Masaki Kumanoya ,  Kazuyasu Fujishima

IPC: H01L27/04 ,  G11C11/404 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC classification number: G11C11/404 ,  H01L27/10817

Abstract: A semiconductor memory device having a storage region constituted with the arrangement of a plurality of memory cells on a main surface of a semiconductor substrate. Each memory cell includes a switching element and a passive element for signal retention connected to the switching element, for retaining the electric charges transferred from the switching element. The passive element includes a central electrode having a generally columnar shape provided protruded on the main surface in a first direction away from the main surface, and the fins constituted with a conductor extending in the first direction and protruded from the outer periphery of the central electrode. Owing to the existence of the fins, the surface area of a signal storage electrode of the passive element is increased. In other words, the quantity of electric charges to be stored is increased.

Abstract translation: 一种半导体存储器件，具有由半导体衬底的主表面上的多个存储单元的配置构成的存储区域。 每个存储单元包括开关元件和用于信号保持的无源元件，连接到开关元件，用于保持从开关元件传递的电荷。 无源元件包括中心电极，该中心电极具有大致圆柱形形状，该主体形状在远离主表面的第一方向上在主表面上突出，并且散热片由沿第一方向延伸并从中心电极的外周突出的导体构成 。 由于鳍的存在，无源元件的信号存储电极的表面积增加。 换句话说，要储存的电荷量增加。