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    Method and apparatus for driving word line in block access memory
    1.
    发明授权
    Method and apparatus for driving word line in block access memory 失效
    用于在块存取存储器中驱动字线的方法和装置

    公开(公告)号：US5371714A

    公开(公告)日：1994-12-06

    申请号：US26225

    申请日：1993-02-26

    Applicant: Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka

    Inventor： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka

    IPC: G11C7/10 ,  G11C8/14 ,  G11C8/18 ,  G11C8/00

    CPC classification number: G11C8/14 ,  G11C7/1036 ,  G11C7/1039 ,  G11C8/18 ,  H01L2924/01074

    Abstract: In a block access memory in which the memory cell array is divided into a plurality of blocks and data input/output is carried out by block unit, each block is divided into a plurality of subblocks, and the timing of activating the word line and the timing of activating the sense amplifier are made different for each subblock in the block in which the selected word line is included, whereby the peak current associated with the bit line charge/discharge at the time of activating the sense amplifiers is reduced.

    Abstract translation: 在其中存储单元阵列被划分成多个块并且通过块单元执行数据输入/输出的块存取存储器中，每个块被划分成多个子块，并且激活字线和 激活读出放大器的定时对于其中包括所选择的字线的块中的每个子块而言是不同的，从而降低与激活读出放大器时的位线充电/放电相关联的峰值电流。

    Bit line structure for semiconductor memory device with bank separation at cross-over regions
    3.
    发明授权
    Bit line structure for semiconductor memory device with bank separation at cross-over regions 失效
    半导体存储器件的位线结构，在交叉区域具有银行分离

    公开(公告)号：US5461589A

    公开(公告)日：1995-10-24

    申请号：US145733

    申请日：1993-11-04

    Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    IPC: G11C5/06 ,  G11C7/18 ,  G11C7/02

    CPC classification number: G11C5/063 ,  G11C7/18

    Abstract: A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines.Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers.More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.

    Abstract translation: 一种折叠位线结构的半导体存储器件，其在位线对中的每一个的至少一部分中具有交叉部分，使得与相邻位线对的耦合电容值相对于成对位线彼此相等。 优选地，各位线对被等分成4N，并且在分割点处提供交叉部分，使得在相同分割点处具有交叉部分的位线对被布置在交替的位线对上。 优选地，十字部分设置在用于形成恢复电路或感测放大器的区域中。 更优选地，通过所选字线的位置选择用于选择用于提供参考电位的虚拟单元的虚拟字线。

    Bit line structure for semiconductor memory device
    4.
    发明授权
    Bit line structure for semiconductor memory device 失效
    半导体存储器件的位线结构

    公开(公告)号：US5280443A

    公开(公告)日：1994-01-18

    申请号：US028906

    申请日：1993-03-08

    Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    IPC: G11C5/06 ,  G11C7/18

    CPC classification number: G11C5/063 ,  G11C7/18

    Abstract: A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines. Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines. Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers. More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.

    Abstract translation: 一种折叠位线结构的半导体存储器件，其在位线对中的每一个的至少一部分中具有交叉部分，使得与相邻位线对的耦合电容值相对于成对位线彼此相等。 优选地，各位线对被等分成4N，并且在分割点处提供交叉部分，使得在相同分割点处具有交叉部分的位线对被布置在交替的位线对上。 优选地，十字部分设置在用于形成恢复电路或感测放大器的区域中。 更优选地，通过所选字线的位置选择用于选择用于提供参考电位的虚拟单元的虚拟字线。

    Automated error detection for multiple block memory array chip and correction thereof
    5.
    发明授权
    Automated error detection for multiple block memory array chip and correction thereof 失效
    多块存储器阵列芯片的自动错误检测及其校正

    公开(公告)号：US4918692A

    公开(公告)日：1990-04-17

    申请号：US201413

    申请日：1988-06-02

    Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    IPC: G11C29/00 ,  G06F11/10 ,  G11C11/401 ,  G11C29/04 ,  G11C29/42 ,  H01L27/10

    CPC classification number: G06F11/1008 ,  G06F11/1076

    Abstract: A semiconductor memory device comprises a plurality of memory cell array blocks. An address changing system is provided in each memory cell array block. The same address signal is applied to these address changing systems. Each address changing system comprises a plurality of linking devices. By previously blowing out any of the linking devices in each address changing system, an externally applied address signal is changed with another address signal to be applied to a corresponding memory cell array block.

    Abstract translation: 半导体存储器件包括多个存储单元阵列块。 在每个存储单元阵列块中提供地址改变系统。 相同的地址信号被应用于这些地址改变系统。 每个地址改变系统包括多个链接装置。 通过先前吹出每个地址改变系统中的任何链接装置，外部施加的地址信号被改变以应用于相应的存储单元阵列块的另一个地址信号。

    Bit line structure for semiconductor memory device including cross-points and multiple interconnect layers
    7.
    发明授权
    Bit line structure for semiconductor memory device including cross-points and multiple interconnect layers 失效
    包括交叉点和多个互连层的半导体存储器件的位线结构

    公开(公告)号：US5214601A

    公开(公告)日：1993-05-25

    申请号：US876690

    申请日：1992-04-28

    Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    IPC: G11C5/06 ,  G11C7/18

    CPC classification number: G11C5/063 ,  G11C7/18

    Abstract: A semiconductor memory device of folded bit line structure includes a cross portion in at least one portion of each bit line pair so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines. Preferably, the respective bit line pairs are equally divided into 4N (N being an integer), although advantages of the invention may be obtained with division of the bit lines into 3N, and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines. In a preferred embodiment, the cross parts are provided in regions for forming restore circuits or sense amplifiers. In a further embodiment, a dummy word line for selecting dummy cells for providing a reference potential is selected according to the position of a selected word line.

    Abstract translation: 折叠位线结构的半导体存储器件包括每个位线对的至少一部分中的交叉部分，使得与相邻位线对的耦合电容值相对于成对的位线彼此相等。 优选地，各位线对被均等地划分为4N（N是整数），尽管可以通过将位线划分为3N来获得本发明的优点，并且在分割点处提供交叉部分，使得位线对 将相同分割点处的交叉部分布置在交替的位线对上。 在优选实施例中，交叉部分设置在用于形成恢复电路或感测放大器的区域中。 在另一实施例中，根据所选字线的位置选择用于选择用于提供参考电位的虚拟单元的虚拟字线。

    Semiconductor memory device with cache memory addressable by block within each column
    8.
    发明授权
    Semiconductor memory device with cache memory addressable by block within each column 失效
    具有高速缓存存储器的半导体存储器件可在每列内通过块寻址

    公开(公告)号：US4926385A

    公开(公告)日：1990-05-15

    申请号：US228589

    申请日：1988-08-05

    Applicant: Kazuyasu Fujishima ,  Hideto Hidaka ,  Mikio Asakura ,  Yoshio Matsuda

    Inventor： Kazuyasu Fujishima ,  Hideto Hidaka ,  Mikio Asakura ,  Yoshio Matsuda

    IPC: G11C11/401 ,  G06F12/08 ,  G11C7/10 ,  G11C8/12 ,  G11C11/41

    CPC classification number: G11C7/103 ,  G06F12/0893 ,  G11C8/12

    Abstract: A semiconductor memory includes a memory cell array having a plurality of bit lines and a plurality of word lines arranged intersecting with the bit lines. A plurality of memory cells are arranged at intersections of the bit lines and the word lines, respectively. Word line selecting circuitry selects one of the word lines responsive to a row address and reads out to each of the bit lines information stored in the memory cell associated with the selected word line. A plurality of sense amplifiers are associated with corresponding rows of the memory for detecting and amplifying the information stored in respective memory cells. A first column selector circuit selects the sense amplifiers corresponding to a column address when the column address is applied and reads information held in the sense amplifier. Blocks are formed by dividing the memory cell array into groups of bit lines, each of the groups comprising a predetermined number of bit lines with block information transferred simultaneously from corresponding ones of the groups of bit lines of a selected block when the column address corresponding to the selected block is applied. Data registers hold information of an associated block. A second column selector reads data corresponding to the column address from the data register when the column address is applied.

    Abstract translation: 半导体存储器包括具有多个位线的存储单元阵列和与位线相交的多个字线。 多个存储单元分别布置在位线和字线的交点处。 字线选择电路响应于行地址选择一个字线，并读出存储在与所选字线相关联的存储单元中的每一个位线信息。 多个读出放大器与存储器的相应行相关联，用于检测和放大存储在相应存储单元中的信息。 当应用列地址时，第一列选择器电路选择对应于列地址的读出放大器，并读取保持在读出放大器中的信息。 通过将存储单元阵列划分成位线组来形成块，每个组包括预定数量的位线，其中块信息同时从对应于所选块的位线的位线的相应位组传送 应用所选的块。 数据寄存器保存相关块的信息。 当应用列地址时，第二列选择器从数据寄存器读取与列地址对应的数据。

    Bit line structure for semiconductor memory device
    9.
    发明授权
    Bit line structure for semiconductor memory device 失效

    公开(公告)号：US5550769A

    公开(公告)日：1996-08-27

    申请号：US336114

    申请日：1994-11-04

    Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    IPC: G11C5/06 ,  G11C7/18 ,  G11C11/24

    CPC classification number: G11C5/063 ,  G11C7/18

    Abstract: A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines.Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers.More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.

    Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof
    10.
    发明授权
    Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof 失效
    具有集成在同一芯片上的作为高速缓存存储器的SRAM的半导体存储器件及其操作方法

    公开(公告)号：US5509132A

    公开(公告)日：1996-04-16

    申请号：US283487

    申请日：1994-08-01

    Applicant: Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Mikio Asakura

    Inventor： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Mikio Asakura

    IPC: G06F12/08 ,  G11C7/10 ,  G11C8/00 ,  G11C11/401 ,  G11C11/41

    CPC classification number: G06F12/0893 ,  G11C7/1051

    Abstract: A cache DRAM (100) includes a DRAM memory array (11) accessed by a row address signal and a column address signal, an SRAM memory array (21) accessed by the column address signal, and an ECC circuit (30). The DRAM memory array (11) is divided into a plurality of blocks (B1 to B64), each including a plurality of columns. The SRAM memory array (21) includes 4 ways (W1 to W4). In determining a cache hit/cache miss, a column address signal is inputted. Consequently, the SRAM memory array (21) is accessed and data are read from each of the ways. When a cache hit occurs, one way is selected in response to an externally applied way address signal, and data from that way are outputted. When a cache miss occurs, the column address signal is latched and the row address signal is applied. The DRAM array (11) is accessed in accordance with the row address signal and the latched column address signal.

    Abstract translation: 缓存DRAM（100）包括通过行地址信号和列地址信号访问的DRAM存储器阵列（11），由列地址信号访问的SRAM存储器阵列（21）和ECC电路（30）。 DRAM存储器阵列（11）被分成多个块（B1至B64），每个块包括多个列。 SRAM存储器阵列（21）包括4路（W1至W4）。 在确定高速缓存命中/高速缓存未命中时，输入列地址信号。 因此，访问SRAM存储器阵列（21）并且从每种方式读取数据。 当发生高速缓存命中时，响应于外部施加的方式地址信号选择一种方式，并且从该方式输出数据。 当发生高速缓存未命中时，锁存列地址信号并应用行地址信号。 根据行地址信号和锁存列地址信号来访问DRAM阵列（11）。

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