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    Method for depositing a thin film
    2.
    发明授权
    Method for depositing a thin film 失效
    沉积薄膜的方法

    公开(公告)号：US6069094A

    公开(公告)日：2000-05-30

    申请号：US924304

    申请日：1997-09-05

    Applicant: Hideki Matsumura ,  Akira Izumi ,  Atsushi Masuda ,  Yasunobu Nashimoto ,  Yosuke Miyoshi ,  Shuji Nomura ,  Kazuo Sakurai ,  Shouichi Aoshima

    Inventor： Hideki Matsumura ,  Akira Izumi ,  Atsushi Masuda ,  Yasunobu Nashimoto ,  Yosuke Miyoshi ,  Shuji Nomura ,  Kazuo Sakurai ,  Shouichi Aoshima

    IPC: H01L21/205 ,  C23C16/02 ,  C23C16/44 ,  H01L21/28 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318

    CPC classification number: C23C16/44 ,  C23C16/0236 ,  H01L21/28264 ,  H01L21/3185

    Abstract: This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 10.sup.12 eV .sup.-1 cm.sup.-2 or less, which is brought by the above pre-treatment in the insulator film deposition process.

    Abstract translation: 本发明公开了一种方法和装置，其中在使用催化气相反应的薄膜沉积在基板上之前进行降低界面密度的预处理。 催化气相反应是通过设置在基板表面附近的热催化体被提供给基板的处理气体产生的。 在该预处理之后进行在基板表面上的薄膜沉积。 热催化体由钨，钼，钽，钛或钒制成，并被加热器加热。 并且，本发明还公开了一种具有半导体 - 绝缘体结的半导体器件，其界面电平密度为1012eV -1cm-2或更小，这是通过上述绝缘膜沉积工艺中的预处理所带来的。

    Method and apparatus for depositing a thin film, and semiconductor device having a semiconductor-insulator junction
    3.
    发明授权
    Method and apparatus for depositing a thin film, and semiconductor device having a semiconductor-insulator junction 有权
    用于沉积薄膜的方法和装置以及具有半导体 - 绝缘体结的半导体器件

    公开(公告)号：US06723664B2

    公开(公告)日：2004-04-20

    申请号：US10041609

    申请日：2002-01-10

    Applicant: Hideki Matsumura ,  Akira Izumi ,  Atsushi Masuda ,  Yasunobu Nashimoto ,  Yosuke Miyoshi ,  Shuji Nomura ,  Kazuo Sakurai ,  Shouichi Aoshima

    Inventor： Hideki Matsumura ,  Akira Izumi ,  Atsushi Masuda ,  Yasunobu Nashimoto ,  Yosuke Miyoshi ,  Shuji Nomura ,  Kazuo Sakurai ,  Shouichi Aoshima

    IPC: H01L2131

    CPC classification number: C23C16/44 ,  C23C16/0236 ,  H01L21/28264 ,  H01L21/3185

    Abstract: This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 1012 eV −1cm−2 or less, which is brought by the above pre-treatment in the insulator film deposition process.

    Abstract translation: 本发明公开了一种方法和装置，其中在使用催化气相反应的薄膜沉积在基板上之前进行降低界面密度的预处理。 催化气相反应是通过设置在基板表面附近的热催化体被提供给基板的处理气体产生的。 在该预处理之后进行在基板表面上的薄膜沉积。 热催化体由钨，钼，钽，钛或钒制成，并被加热器加热。 并且，本发明还公开了一种具有半导体 - 绝缘体结的半导体器件，其界面密度为10 12 eV -1 cm -2以下，这是通过上述预处理在绝缘体中产生的 薄膜沉积工艺。

    Fabrication method of field-effect transistor
    6.
    发明授权
    Fabrication method of field-effect transistor 失效
    场效应晶体管的制造方法

    公开(公告)号：US5500381A

    公开(公告)日：1996-03-19

    申请号：US413616

    申请日：1995-03-30

    Applicant: Takayoshi Yoshida ,  Yasunobu Nashimoto

    Inventor： Takayoshi Yoshida ,  Yasunobu Nashimoto

    IPC: H01L29/812 ,  H01L21/285 ,  H01L21/335 ,  H01L21/338 ,  H01L29/778

    CPC classification number: H01L29/66462 ,  H01L21/28587 ,  H01L29/7787 ,  Y10S148/10

    Abstract: A fabrication method of a FET that enables to realize a shorter length between a source-side edge of a recess and an opposing edge of a gate electrode at a higher accuracy than the accuracy limit of the present lithography technique, i.e., about .+-.0.1 .mu.m. After channel, carrier-supply, and contact layers are epitaxially grown on a semiconductor substrate in this order, a patterned insulator layer is formed on the contact layer. Using the insulator layer as a mask, the contact layer is isotropically etched to form a symmetrical recess on the underlying carrier-supply layer. One of the ends of the contact layer facing the symmetrical recess is etched again to make it asymmetric. During the etching processes, the underlying carrier-supply layer is almost never etched due to large etch rate differences for the contact layer and the carrier-supply layer. A patterned conductor layer is formed on the patterned insulator layer to form the gate electrode in Schottky contact with the carrier-supply layer. After removing the insulator layer, and source and drain electrodes are formed on the contact layer. An etch-stop layer is additionally formed between the carrier-supply layer and the contact layer.

    Abstract translation: 一种FET的制造方法，其能够以比本光刻技术的精度极限更高的精度实现凹部的源极侧边缘和栅电极的相对边缘之间的更短的长度，即约+/- 0.1亩。 在半导体衬底上依次外延生长通道，载流子供应和接触层之后，在接触层上形成图案化的绝缘体层。 使用绝缘体层作为掩模，接触层被各向同性地蚀刻以在下层载体供给层上形成对称的凹部。 面对对称凹部的接触层的端部之一被再次蚀刻以使其不对称。 在蚀刻工艺期间，由于接触层和载体供应层的较大的蚀刻速率差，底层载体供应层几乎不被蚀刻。 在图案化的绝缘体层上形成图案化导体层，以形成与载体供给层肖特基接触的栅电极。 在去除绝缘体层之后，在接触层上形成源极和漏极。 在载体供给层和接触层之间另外形成蚀刻停止层。

    Field effect transistor
    7.
    发明授权
    Field effect transistor 有权
    场效应晶体管

    公开(公告)号：US06483135B1

    公开(公告)日：2002-11-19

    申请号：US09383983

    申请日：1999-08-26

    Applicant: Masashi Mizuta ,  Masaaki Kuzuhara ,  Yasunobu Nashimoto ,  Kazunori Asano ,  Yosuke Miyoshi ,  Yasunori Mochizuki

    Inventor： Masashi Mizuta ,  Masaaki Kuzuhara ,  Yasunobu Nashimoto ,  Kazunori Asano ,  Yosuke Miyoshi ,  Yasunori Mochizuki

    IPC: H01L2980

    CPC classification number: H01L29/402 ,  H01L29/42316 ,  H01L29/8128

    Abstract: A field effect transistor includes a semiconductor substrate with a channel layer being formed on its surface, a source electrode and a drain electrode formed at a distance on said semiconductor substrate, and a gate electrode placed between the source electrode and the drain electrode and making a Schottky junction with the channel layer. The gate electrode is provided with an overhanging field plate section and between the field plate section and the channel layer, there is laid a dielectric film. When the relative permittivity and the film thickness of the dielectric film are denoted by ∈ and t (nm), respectively, the following condition is satisfied 5≦∈

    Abstract translation: 场效应晶体管包括在其表面上形成有沟道层的半导体衬底，在所述半导体衬底上形成一定距离的源电极和漏电极，以及放置在源电极和漏极之间的栅电极， 与通道层的肖特基结。 栅电极设置有突出场板部分，并且在场板部分和沟道层之间设置介电膜。 当介电膜的相对介电常数和膜厚分别表示为in和t（nm）时，满足以下条件5 <=在<8且100

    Method and apparatus for depositing a thin film, and semiconductor device having a semiconductor-insulator junction
    8.
    发明授权
    Method and apparatus for depositing a thin film, and semiconductor device having a semiconductor-insulator junction 失效
    用于沉积薄膜的方法和装置以及具有半导体 - 绝缘体结的半导体器件

    公开(公告)号：US06349669B1

    公开(公告)日：2002-02-26

    申请号：US09102665

    申请日：1998-06-23

    Applicant: Hideki Matsumura ,  Akira Izumi ,  Atsushi Masuda ,  Yasunobu Nashimoto ,  Yosuke Miyoshi ,  Shuji Nomura ,  Kazuo Sakurai ,  Shouichi Aoshima

    Inventor： Hideki Matsumura ,  Akira Izumi ,  Atsushi Masuda ,  Yasunobu Nashimoto ,  Yosuke Miyoshi ,  Shuji Nomura ,  Kazuo Sakurai ,  Shouichi Aoshima

    IPC: C23C1600

    CPC classification number: C23C16/44 ,  C23C16/0236 ,  H01L21/28264 ,  H01L21/3185

    Abstract: This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 1012 eV−1 cm−2 or less, which is brought by the above pre-treatment in the insulator film deposition process.

    Abstract translation: 本发明公开了一种方法和装置，其中在使用催化气相反应的薄膜沉积在基板上之前进行降低界面密度的预处理。 催化气相反应是通过设置在基板表面附近的热催化体被提供给基板的处理气体产生的。 在该预处理之后进行在基板表面上的薄膜沉积。 热催化体由钨，钼，钽，钛或钒制成，并被加热器加热。 而且，本发明还公开了一种具有半导体 - 绝缘体结的半导体器件，其界面电平密度为1012eV-1cm-2或更低，这是通过上述绝缘膜沉积工艺中的预处理而得到的。

    Field effect transistor and its manufacturing method
    9.
    发明授权
    Field effect transistor and its manufacturing method 失效
    场效应晶体管及其制造方法

    公开(公告)号：US06242765B1

    公开(公告)日：2001-06-05

    申请号：US08562640

    申请日：1995-11-27

    Applicant: Yasunobu Nashimoto

    Inventor： Yasunobu Nashimoto

    IPC: H01L310328

    CPC classification number: B82Y10/00 ,  H01L29/775 ,  H01L29/7787

    Abstract: A hetero-junctioned FET having as its conductive channel a highly mobile electron accumulated layer where electrons are one-dimensionally distributed. This FET is provided with first and second semiconductor layers which, formed on a semiconductor substrate, are different from each other in electron affinity and produce a semiconductor hetero junction, a source electrode and a drain electrode formed on either the first or second semiconductor layer, multiple fine damaged-area stripes formed near the interface of the hetero junction within the first semiconductor layer in the channel area between the source and drain electrodes, and a conductive channel of multiple fine electron accumulated-layer stripes generatred at the locations other than those facing the damaged areas near the interface of the hetero junction within the second semiconductor layer. In this FET, the damaged areas selectively formed at the locations other than those of the conductive channel areas between the source and drain electrodes eliminates, at the locations corresponding to the damaged areas, the electron accumulated layers generated due to a semiconductor hetero junction to function as a conductive channel. This enables a conductive channel to be divided into strips each 0.1 &mgr;m or less wide.

    Abstract translation: 具有作为其导电通道的异质结的FET是电子一维分布的高度可移动的电子积累层。 该FET设置有形成在半导体衬底上的电子亲和力彼此不同的第一和第二半导体层，并且形成在第一或第二半导体层上的半导体异质结，源电极和漏电极， 在源极和漏极之间的沟道区域内形成在第一半导体层内的异质结的界面附近的多个细小的损伤区域条纹，以及在除了面对之外的位置处产生的多个细小的电子积累层条纹的导电沟道 在第二半导体层内的异质结界面附近的损伤区域。 在该FET中，选择性地形成在源电极和漏电极之间的导电沟道区域以外的位置处的损坏区域在与损坏区域相对应的位置处消除由于半导体异质结而产生的电子累积层起作用 作为导电通道。 这使得导电通道能够被分成0.1μm或更小宽度的条带。

    Junction type field-effect transistor
    10.
    发明授权
    Junction type field-effect transistor 失效
    结型场效应晶体管

    公开(公告)号：US5661318A

    公开(公告)日：1997-08-26

    申请号：US395802

    申请日：1995-02-28

    Applicant: Yasunobu Nashimoto

    Inventor： Yasunobu Nashimoto

    IPC: H01L21/337 ,  H01L29/10 ,  H01L29/808 ,  H01L31/0328 ,  H01L29/80

    CPC classification number: H01L29/1066 ,  H01L29/8083

    Abstract: A junction type field-effect transistor in accordance with the invention includes a multi-layer structure which includes a first undoped semiconductor layer, a first first-conductive type semiconductor layer and a second undoped semiconductor layer. These layers are deposited and epitaxially grown in this order on a surface of a semiconductor substrate. A part of the first first-conductive type semiconductor layer is exposed outside in a surface of the multi-layer structure. A second-conductive semiconductor layer is joined to the multi-layer structure through the surface of said multi-layer structure. A drain electrode line and a source electrode line are kept in ohmic contact with the second-conductive type semiconductor layer, and are disposed at opposite sides of a location at which the first first-conductive type semiconductor layer is joined to the second-conductive type semiconductor layer. The invention makes it possible to form the first first-conductive type semiconductor layer thinner, and thereby achieve a gate length shorter than a minimum length achievable by lithography technique.

    Abstract translation: 根据本发明的结型场效应晶体管包括多层结构，其包括第一未掺杂半导体层，第一第一导电类型半导体层和第二未掺杂半导体层。 这些层在半导体衬底的表面上依次沉积并外延生长。 第一第一导电类型半导体层的一部分在多层结构的表面中暴露在外部。 第二导电半导体层通过所述多层结构的表面连接到多层结构。 漏电极线和源电极线与第二导电型半导体层保持欧姆接触，并且设置在第一第一导电型半导体层与第二导电型半导体层接合的位置的相对侧 半导体层。 本发明使得可以形成更薄的第一第一导电型半导体层，从而实现比通过光刻技术可实现的最小长度短的栅极长度。

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