公开(公告)号：US08803293B2

公开(公告)日：2014-08-12

申请号：US13469258

申请日：2012-05-11

Applicant: Tom Zhong ,  Kenlin Huang ,  Chyu-Jiuh Torng

Inventor： Tom Zhong ,  Kenlin Huang ,  Chyu-Jiuh Torng

IPC: H01L29/06

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A method of forming a thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate so that the thin-film deposition is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer is formed on the CMOS substrate and is patterned by either forming undercut trenches extending into its upper surface or by fabricating T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage.

Abstract translation: 在晶片级CMOS衬底上形成诸如MTJ（磁性隧道结）层的薄膜沉积的方法，使得薄膜沉积被壁或沟槽分段，并且不受薄膜应力的影响 晶圆翘曲或其他后续退火工艺。 在CMOS衬底上形成界面层，并且通过形成延伸到其上表面的底切沟槽或通过制造沿其上表面延伸的T形壁而被图案化。 薄膜连续地沉积在图案化表面上，于是沟槽或壁分隔沉积物并用作应力消除机制，以消除作为诸如由晶片翘曲引起的应力的加工的不利影响。

公开(公告)号：US08524511B1

公开(公告)日：2013-09-03

申请号：US13571675

申请日：2012-08-10

Applicant: Tom Zhong ,  Vinh Lam ,  Zhongjian Teng

Inventor： Tom Zhong ,  Vinh Lam ,  Zhongjian Teng

IPC: H01L21/00

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A CMOS device is provided in a substrate. A magnetic tunnel junction (MTJ) is provided over the CMOS device and connected to the CMOS device by a metal ring contact wherein a dielectric or other filling material forms the center of the metal ring contact and wherein a bottom of the metal ring contact underlying said filling material is metal.

Abstract translation: 在衬底中提供CMOS器件。 磁性隧道结（MTJ）设置在CMOS器件上并通过金属环接触连接到CMOS器件，其中电介质或其它填充材料形成金属环接触的中心，并且其中金属环的底部接触在所述 填充材料是金属。

公开(公告)号：US20110133300A1

公开(公告)日：2011-06-09

申请号：US12927670

申请日：2010-11-19

Applicant: Rongfu Xiao ,  Cheng T. Horng ,  Ru-Ying Tong ,  Chyu-Jinh Torng ,  Tom Zhong ,  Witold Kula ,  Terry Kin Ting Ko ,  Wei Cao ,  Wai-Ming J. Kan ,  Liubo Hong

Inventor： Rongfu Xiao ,  Cheng T. Horng ,  Ru-Ying Tong ,  Chyu-Jinh Torng ,  Tom Zhong ,  Witold Kula ,  Terry Kin Ting Ko ,  Wei Cao ,  Wai-Ming J. Kan ,  Liubo Hong

IPC: H01L29/82

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/08

Abstract: A multi-layered bottom electrode for an MTJ device on a silicon nitride substrate is described. It comprises a bilayer of alpha tantalum on ruthenium which in turn lies on a nickel chrome layer over a second tantalum layer.

Abstract translation: 描述了用于氮化硅衬底上的MTJ器件的多层底电极。 它包括在钌上的α钽的双层，其又位于第二钽层上的镍铬层上。

公开(公告)号：US07919407B1

公开(公告)日：2011-04-05

申请号：US12590945

申请日：2009-11-17

Applicant: Tom Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu ,  Adam Zhong ,  Chyu-Jiuh Torng

Inventor： Tom Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu ,  Adam Zhong ,  Chyu-Jiuh Torng

IPC: H01L21/4763

CPC classification number: H01L21/76807 ,  H01L21/76816 ,  H01L27/228

Abstract: Described herein are novel, cost effective and scalable methods for integrating a CMOS level with a memory cell level to form a field induced MRAM device. The memory portion of the device includes N parallel word lines, which may be clad, overlaid by M parallel bit lines orthogonal to the word lines and individual patterned memory cells formed on previously patterned electrodes at the N×M intersections of the two sets of lines. The memory portion is integrated with a CMOS level and the connection between levels is facilitated by the formation of interconnecting vias between the N×M electrodes and corresponding pads in the CMOS level and by word line connection pads in the memory device level and corresponding metal pads in the CMOS level. Of particular importance are process steps that replace single damascene formations by dual damascene formations, different process steps for the formation of clad and unclad word lines and the formation of patterned electrodes for the memory cells prior to the patterning of the cells themselves.

Abstract translation: 这里描述了用于将CMOS电平与存储器单元级集成以形成场感应MRAM器件的新颖的，成本有效的和可扩展的方法。 器件的存储器部分包括N个并行字线，其可以由两条垂直于字线的M个并行位线和在两组线的N×M个交点处形成在先前图案化电极上的各个图案化存储单元重叠 。 存储器部分与CMOS电平集成，并且通过在CMOS电平中的N×M电极和相应焊盘之间的互连通孔以及存储器件级中的字线连接焊盘和对应的金属焊盘 在CMOS级别。 特别重要的是通过双镶嵌结构取代单个镶嵌地层的工艺步骤，用于形成包层和未包层字线的不同工艺步骤以及在细胞本身的图案化之前形成记忆单元的图案化电极。

公开(公告)号：US20110076785A1

公开(公告)日：2011-03-31

申请号：US12927615

申请日：2010-11-19

Applicant: Rongfu Xiao ,  Cheng T. Horng ,  Ru-Ying Tong ,  Chyu-Jinh Torng ,  Tom Zhong ,  Witold Kula ,  Terry Kin Ting Ko ,  Wei Cao ,  Wai-Ming J. Kan ,  Liubo Hong

Inventor： Rongfu Xiao ,  Cheng T. Horng ,  Ru-Ying Tong ,  Chyu-Jinh Torng ,  Tom Zhong ,  Witold Kula ,  Terry Kin Ting Ko ,  Wei Cao ,  Wai-Ming J. Kan ,  Liubo Hong

IPC: H01L21/00

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/08

Abstract: Formation of a bottom electrode for an MTJ device on a silicon nitride substrate is facilitated by including a protective coating that is partly consumed during etching of the alpha tantalum portion of said bottom electrode. Adhesion to SiN is enhanced by using a TaN/NiCr bilayer as “glue”.

Abstract translation: 在氮化硅衬底上形成用于MTJ器件的底部电极通过包括在所述底部电极的α钽部分的蚀刻期间部分消耗的保护涂层来促进。 通过使用TaN / NiCr双层作为“胶”来增强对SiN的附着力。

公开(公告)号：US20090173977A1

公开(公告)日：2009-07-09

申请号：US12006889

申请日：2008-01-07

Applicant: Rongfu Xiao ,  Chyu-Jiuh Torng ,  Tom Zhong ,  Witold Kula

Inventor： Rongfu Xiao ,  Chyu-Jiuh Torng ,  Tom Zhong ,  Witold Kula

IPC: H01L43/00 ,  H01L29/82 ,  H01L43/12 ,  H01L21/467

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: An MTJ cell without footings and free from electrical short-circuits across a tunneling barrier layer is formed by using a Ta hard mask layer and a combination of etches. A first etch patterns the Ta hard mask, while a second etch uses O2 applied in a single high power process at two successive different power levels. A first power level of between approximately 200 W and 500 W removes BARC, photoresist and Ta residue from the first etch, the second power level, between approximately 400 W and 600 W continues an etch of the stack layers and forms a protective oxide around the etched sides of the stack. Finally, an etch using a carbon, hydrogen and oxygen gas completes the etch while the oxide layer protects the cell from short-circuits across the lateral edges of the barrier layer.

Abstract translation: 通过使用Ta硬掩模层和蚀刻的组合，形成没有底脚并且穿过隧道势垒层的电短路的MTJ电池。 第一蚀刻图案Ta硬掩模，而第二蚀刻使用在两个连续的不同功率水平下在单个高功率过程中施加的O2。 在大约200W至500W之间的第一功率电平从第一蚀刻去除BARC，光致抗蚀剂和Ta残留物，第二功率电平在大约400W至600W之间，继续蚀刻叠层，并在其周围形成保护氧化物 蚀刻边的堆叠。 最后，使用碳，氢和氧气的蚀刻完成了蚀刻，而氧化物层保护电池免受横跨阻挡层的侧边缘的短路。

公开(公告)号：US07476919B2

公开(公告)日：2009-01-13

申请号：US11418910

申请日：2006-05-05

Applicant: Liubo Hong ,  Tom Zhong ,  Lin Yang

Inventor： Liubo Hong ,  Tom Zhong ,  Lin Yang

IPC: H01L27/108

CPC classification number: G11C11/16 ,  H01L27/222 ,  H01L43/12

Abstract: An MRAM structure is disclosed where the distance from a bit line or word line to an underlying free layer in an MTJ is small and well controlled. As a result, the bit line or word line switching current is reduced and tightly distributed for better device performance. A key feature in the method of forming the MRAM cell structure is a two step planarization of an insulation layer deposited on the MTJ array. A CMP step flattens the insulation layer at a distance about 60 to 200 Angstroms above the cap layer in the MTJ. Then an etch back step thins the insulation layer to a level about 50 to 190 Angstroms below the top of the cap layer. Less than 5 Angstroms of the cap layer is removed. The distance variation from the free layer to an overlying bit line or word line is within +/−5 Angstroms.

Abstract translation: 公开了一种MRAM结构，其中从位线或字线到MTJ中的下游自由层的距离小且受到良好控制。 因此，位线或字线切换电流减少并且分布紧密，从而更好的器件性能。 形成MRAM单元结构的方法中的一个关键特征是沉积在MTJ阵列上的绝缘层的两步平面化。 CMP步骤在MTJ的帽层上方约60至200埃的距离处使绝缘层平坦化。 然后，回蚀步骤将绝缘层沉降到帽层顶部下方约50至190埃的水平。 少于5埃的盖层被去除。 从自由层到上位线或字线的距离变化在+/- 5埃以内。

公开(公告)号：US20080225576A1

公开(公告)日：2008-09-18

申请号：US11724435

申请日：2007-03-15

Applicant: Tom Zhong ,  Terry Kin Ting Ko ,  Chyu-Jiuh Torng ,  Wai-Ming Kan ,  Adam Zhong

Inventor： Tom Zhong ,  Terry Kin Ting Ko ,  Chyu-Jiuh Torng ,  Wai-Ming Kan ,  Adam Zhong

IPC: G11C11/00

CPC classification number: H01L27/222 ,  H01L43/12 ,  Y10S977/935

Abstract: An MTJ pattern layout for a memory device is disclosed that includes two CMP assist features outside active MTJ device blocks. A first plurality of dummy MTJ devices is located in two dummy bands formed around an active MTJ device block. The inner dummy band is separated from the outer dummy band by the MTJ ILD layer and has a MTJ device density essentially the same as the MTJ device block. The outer dummy band has a MTJ device density at least 10% greater than the inner dummy band. The inner dummy band serves to minimize CMP edge effect in the MTJ device block while the outer dummy band improves planarization. A second plurality of dummy MTJ devices is employed in contact pads outside the outer dummy band and is formed between a WL ILD layer and a BIT ILD layer thereby minimizing delamination of the MTJ ILD layer.

Abstract translation: 公开了一种用于存储器件的MTJ图案布局，其包括主动MTJ器件块之外的两个CMP辅助特征。 第一组多个虚拟MTJ设备位于形成在活动MTJ设备块周围的两个虚拟带中。 内部虚拟带通过MTJ ILD层与外部虚拟带分离，并且具有与MTJ器件块基本相同的MTJ器件密度。 外虚拟带具有比内虚拟带大至少10％的MTJ装置密度。 内部虚拟带用于最小化MTJ器件块中的CMP边缘效应，而外部虚拟带改善了平坦化。 在外虚拟带外部的接触焊盘中采用第二多个虚拟MTJ器件，并且形成在WL ILD层和BIT ILD层之间，从而最小化MTJ ILD层的分层。

公开(公告)号：US20060209591A1

公开(公告)日：2006-09-21

申请号：US11418910

申请日：2006-05-05

Applicant: Liubo Hong ,  Tom Zhong ,  Lin Yang

Inventor： Liubo Hong ,  Tom Zhong ,  Lin Yang

IPC: G11C11/15

CPC classification number: G11C11/16 ,  H01L27/222 ,  H01L43/12

Abstract: An MRAM structure is disclosed where the distance from a bit line or word line to an underlying free layer in an MTJ is small and well controlled. As a result, the bit line or word line switching current is reduced and tightly distributed for better device performance. A key feature in the method of forming the MRAM cell structure is a two step planarization of an insulation layer deposited on the MTJ array. A CMP step flattens the insulation layer at a distance about 60 to 200 Angstroms above the cap layer in the MTJ. Then an etch back step thins the insulation layer to a level about 50 to 190 Angstroms below the top of the cap layer. Less than 5 Angstroms of the cap layer is removed. The distance variation from the free layer to an overlying bit line or word line is within +/−5 Angstroms.

公开(公告)号：US20050260773A1

公开(公告)日：2005-11-24

申请号：US10849311

申请日：2004-05-19

Applicant: Liubo Hong ,  Tom Zhong ,  Lin Yang

Inventor： Liubo Hong ,  Tom Zhong ,  Lin Yang

IPC: G11C11/16 ,  H01L21/00 ,  H01L27/22 ,  H01L43/12

CPC classification number: G11C11/16 ,  H01L27/222 ,  H01L43/12

Abstract: An MRAM structure is disclosed where the distance from a bit line or word line to an underlying free layer in an MTJ is small and well controlled. As a result, the bit line or word line switching current is reduced and tightly distributed for better device performance. A key feature in the method of forming the MRAM cell structure is a two step planarization of an insulation layer deposited on the MTJ array. A CMP step flattens the insulation layer at a distance about 60 to 200 Angstroms above the cap layer in the MTJ. Then an etch back step thins the insulation layer to a level about 50 to 190 Angstroms below the top of the cap layer. Less than 5 Angstroms of the cap layer is removed. The distance variation from the free layer to an overlying bit line or word line is within +/−5 Angstroms.

Abstract translation: 公开了一种MRAM结构，其中从位线或字线到MTJ中的下游自由层的距离小且受到良好控制。 因此，位线或字线切换电流减少并且分布紧密，从而更好的器件性能。 形成MRAM单元结构的方法中的一个关键特征是沉积在MTJ阵列上的绝缘层的两步平面化。 CMP步骤在MTJ的帽层上方约60至200埃的距离处使绝缘层平坦化。 然后，回蚀步骤将绝缘层沉降到帽层顶部下方约50至190埃的水平。 少于5埃的盖层被去除。 从自由层到上位线或字线的距离变化在+/- 5埃以内。