公开(公告)号：US08803293B2

公开(公告)日：2014-08-12

申请号：US13469258

申请日：2012-05-11

Applicant: Tom Zhong ,  Kenlin Huang ,  Chyu-Jiuh Torng

Inventor： Tom Zhong ,  Kenlin Huang ,  Chyu-Jiuh Torng

IPC: H01L29/06

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A method of forming a thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate so that the thin-film deposition is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer is formed on the CMOS substrate and is patterned by either forming undercut trenches extending into its upper surface or by fabricating T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage.

Abstract translation: 在晶片级CMOS衬底上形成诸如MTJ（磁性隧道结）层的薄膜沉积的方法，使得薄膜沉积被壁或沟槽分段，并且不受薄膜应力的影响 晶圆翘曲或其他后续退火工艺。 在CMOS衬底上形成界面层，并且通过形成延伸到其上表面的底切沟槽或通过制造沿其上表面延伸的T形壁而被图案化。 薄膜连续地沉积在图案化表面上，于是沟槽或壁分隔沉积物并用作应力消除机制，以消除作为诸如由晶片翘曲引起的应力的加工的不利影响。

公开(公告)号：US20140061827A1

公开(公告)日：2014-03-06

申请号：US13597465

申请日：2012-08-29

Applicant: Kenlin Huang ,  Yuan-Tung Chin ,  Tom Zhong ,  Chyu-Jiuh Torng

Inventor： Kenlin Huang ,  Yuan-Tung Chin ,  Tom Zhong ,  Chyu-Jiuh Torng

IPC: H01L29/82 ,  H01L21/8239

CPC classification number: G01R33/098 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/308 ,  H01F41/325 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic thin film deposition is patterned and protected from oxidation during subsequent processes, such as bit line formation, by an oxidation-prevention encapsulation layer of SiN. The SiN layer is then itself protected during the processing by a metal overlayer, preferably of Ta, Al, TiN, TaN or W. A sequence of low pressure plasma etches, using Oxygen, Cl2, BCl3 and C2H4 chemistries provide selectivity of the metal overlayer to various oxide layers and to the photo-resist hard masks used in patterning and metal layer and thereby allow the formation of bit lines while maintaining the integrity of the SiN layer.

Abstract translation: 通过SiN的防氧化封装层，在随后的工艺（例如位线形成）中图案化和保护磁性薄膜沉积物免于氧化。 然后，SiN层在金属覆盖层，优选Ta，Al，TiN，TaN或W的加工过程中自身受到保护。使用氧气，Cl2，BCl3和C2H4化学物质的低压等离子体蚀刻序列提供金属覆层的选择性 到各种氧化物层和用于图案化和金属层中的光刻胶硬掩模，从而允许形成位线，同时保持SiN层的完整性。

公开(公告)号：US20130302912A1

公开(公告)日：2013-11-14

申请号：US13469258

申请日：2012-05-11

Applicant: Tom Zhong ,  Kenlin Huang ,  Chyu-Jiuh Torng

Inventor： Tom Zhong ,  Kenlin Huang ,  Chyu-Jiuh Torng

IPC: H01L21/02

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A method of forming a thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate so that the thin-film deposition is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer is formed on the CMOS substrate and is patterned by either forming undercut trenches extending into its upper surface or by fabricating T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage.

Abstract translation: 在晶片级CMOS衬底上形成诸如MTJ（磁性隧道结）层的薄膜沉积的方法，使得薄膜沉积被壁或沟槽分段，并且不受薄膜应力的影响 晶圆翘曲或其他后续退火工艺。 在CMOS衬底上形成界面层，并且通过形成延伸到其上表面的底切沟槽或通过制造沿其上表面延伸的T形壁而被图案化。 薄膜连续地沉积在图案化表面上，于是沟槽或壁分隔沉积物并用作应力消除机制，以消除作为诸如由晶片翘曲引起的应力的加工的不利影响。

公开(公告)号：US09343463B2

公开(公告)日：2016-05-17

申请号：US12586900

申请日：2009-09-29

Applicant: Tom Zhong ,  Adam Zhong ,  Wai-Ming J. Kan ,  Chyu-Jiuh Torng

Inventor： Tom Zhong ,  Adam Zhong ,  Wai-Ming J. Kan ,  Chyu-Jiuh Torng

IPC: H01L29/66 ,  H01L21/4763 ,  H01L27/105 ,  H01L21/768 ,  H01L23/522 ,  H01L27/22

CPC classification number: H01L27/105 ,  H01L21/76819 ,  H01L21/7684 ,  H01L23/522 ,  H01L27/228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The structure and method of formation of an integrated CMOS level and active device level that can be a memory device level. The integration includes the formation of a “super-flat” interface between the two levels formed by the patterning of a full complement of active and dummy interconnecting vias using two separate patterning and etch processes. The active vias connect memory devices in the upper device level to connecting pads in the lower CMOS level. The dummy vias may extend up to an etch stop layer formed over the CMOS layer or may be stopped at an intermediate etch stop layer formed within the device level. The dummy vias thereby contact memory devices but do not connect them to active elements in the CMOS level.

Abstract translation: 集成CMOS级别和有源器件级别的结构和方法可以是存储器件级。 整合包括通过使用两个单独的图案化和蚀刻工艺对完整的有源和虚拟互连通孔进行图案化形成的两层之间形成“超平面”界面。 有源通孔将上部器件电平的存储器件连接到较低CMOS电平的连接焊盘。 虚拟通孔可以延伸到在CMOS层上形成的蚀刻停止层，或者可以在形成在器件级内的中间蚀刻停止层处停止。 因此，虚拟通孔接触存储器件，但不将它们连接到CMOS电平中的有源元件。

公开(公告)号：US20120085728A1

公开(公告)日：2012-04-12

申请号：US12924873

申请日：2010-10-07

Applicant: Jun Chen ,  Guomin Mao ,  Tom Zhong ,  Wei Cao ,  Yee-Chung Fu ,  Chyu-Jiuh Torng

Inventor： Jun Chen ,  Guomin Mao ,  Tom Zhong ,  Wei Cao ,  Yee-Chung Fu ,  Chyu-Jiuh Torng

IPC: B81C1/00

CPC classification number: B81B3/0045 ,  B81B2201/042 ,  G02B26/0841

Abstract: Two methods of fabricating a MEMS scanning mirror having a tunable resonance frequency are described. The resonance frequency of the mirror is set to a particular value by mass removal from the backside of the mirror during fabrication.

Abstract translation: 描述制造具有可调共振频率的MEMS扫描反射镜的两种方法。 反射镜的共振频率通过在制造期间从反射镜的背面质量去除而被设定为特定的值。

公开(公告)号：US08105948B2

公开(公告)日：2012-01-31

申请号：US12070286

申请日：2008-02-14

Applicant: Adam Zhong ,  Wai-Ming Kan ,  Tom Zhong ,  Chyu-Jiuh Torng

Inventor： Adam Zhong ,  Wai-Ming Kan ,  Tom Zhong ,  Chyu-Jiuh Torng

IPC: H01L21/302

CPC classification number: H01L21/31053 ,  H01L43/12

Abstract: A process is described for making contact to the buried capping layers of GMR and MTJ devices without the need to form and fill via holes. CMP is applied to the structure in three steps: (1) conventional CMP (2) a Highly Selective Slurry (HSS) is substituted for the conventional slurry to just expose the capping layer, and (3) the HSS is diluted and used to clean the surface as well as to cause a slight protrusion of the capping layers above the surrounding dielectric surface, making it easier the contact them without damaging the devices below.

Abstract translation: 描述了与GMR和MTJ装置的掩埋覆盖层接触而不需要形成和填充通孔的方法。 CMP结构分为三个步骤：（1）常规CMP（2）采用高选择性浆料（HSS）代替传统的浆料，仅暴露顶盖层，（3）将HSS稀释并用于清洗 表面以及使覆盖层在周围的电介质表面上稍微突出，使得更容易接触它们而不损坏下面的器件。

公开(公告)号：US07936027B2

公开(公告)日：2011-05-03

申请号：US12006889

申请日：2008-01-07

Applicant: Rongfu Xiao ,  Chyu-Jiuh Torng ,  Tom Zhong ,  Witold Kula

Inventor： Rongfu Xiao ,  Chyu-Jiuh Torng ,  Tom Zhong ,  Witold Kula

IPC: G11C11/02

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: An MTJ cell without footings and free from electrical short-circuits across a tunneling barrier layer is formed by using a Ta hard mask layer and a combination of etches. A first etch patterns the Ta hard mask, while a second etch uses O2 applied in a single high power process at two successive different power levels. A first power level of between approximately 200 W and 500 W removes BARC, photoresist and Ta residue from the first etch, the second power level, between approximately 400 W and 600 W continues an etch of the stack layers and forms a protective oxide around the etched sides of the stack. Finally, an etch using a carbon, hydrogen and oxygen gas completes the etch while the oxide layer protects the cell from short-circuits across the lateral edges of the barrier layer.

Abstract translation: 通过使用Ta硬掩模层和蚀刻的组合，形成没有底脚并且穿过隧道势垒层的电短路的MTJ电池。 第一蚀刻图案Ta硬掩模，而第二蚀刻使用在两个连续的不同功率水平下在单个高功率过程中施加的O2。 在大约200W至500W之间的第一功率电平从第一蚀刻去除BARC，光致抗蚀剂和Ta残留物，第二功率电平在大约400W至600W之间，继续蚀刻叠层，并在其周围形成保护氧化物 蚀刻边的堆叠。 最后，使用碳，氢和氧气的蚀刻完成了蚀刻，而氧化物层保护电池免受横跨阻挡层的侧边缘的短路。

公开(公告)号：US07919407B1

公开(公告)日：2011-04-05

申请号：US12590945

申请日：2009-11-17

Applicant: Tom Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu ,  Adam Zhong ,  Chyu-Jiuh Torng

Inventor： Tom Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu ,  Adam Zhong ,  Chyu-Jiuh Torng

IPC: H01L21/4763

CPC classification number: H01L21/76807 ,  H01L21/76816 ,  H01L27/228

Abstract: Described herein are novel, cost effective and scalable methods for integrating a CMOS level with a memory cell level to form a field induced MRAM device. The memory portion of the device includes N parallel word lines, which may be clad, overlaid by M parallel bit lines orthogonal to the word lines and individual patterned memory cells formed on previously patterned electrodes at the N×M intersections of the two sets of lines. The memory portion is integrated with a CMOS level and the connection between levels is facilitated by the formation of interconnecting vias between the N×M electrodes and corresponding pads in the CMOS level and by word line connection pads in the memory device level and corresponding metal pads in the CMOS level. Of particular importance are process steps that replace single damascene formations by dual damascene formations, different process steps for the formation of clad and unclad word lines and the formation of patterned electrodes for the memory cells prior to the patterning of the cells themselves.

Abstract translation: 这里描述了用于将CMOS电平与存储器单元级集成以形成场感应MRAM器件的新颖的，成本有效的和可扩展的方法。 器件的存储器部分包括N个并行字线，其可以由两条垂直于字线的M个并行位线和在两组线的N×M个交点处形成在先前图案化电极上的各个图案化存储单元重叠 。 存储器部分与CMOS电平集成，并且通过在CMOS电平中的N×M电极和相应焊盘之间的互连通孔以及存储器件级中的字线连接焊盘和对应的金属焊盘 在CMOS级别。 特别重要的是通过双镶嵌结构取代单个镶嵌地层的工艺步骤，用于形成包层和未包层字线的不同工艺步骤以及在细胞本身的图案化之前形成记忆单元的图案化电极。

公开(公告)号：US20090173977A1

公开(公告)日：2009-07-09

申请号：US12006889

申请日：2008-01-07

Applicant: Rongfu Xiao ,  Chyu-Jiuh Torng ,  Tom Zhong ,  Witold Kula

Inventor： Rongfu Xiao ,  Chyu-Jiuh Torng ,  Tom Zhong ,  Witold Kula

IPC: H01L43/00 ,  H01L29/82 ,  H01L43/12 ,  H01L21/467

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: An MTJ cell without footings and free from electrical short-circuits across a tunneling barrier layer is formed by using a Ta hard mask layer and a combination of etches. A first etch patterns the Ta hard mask, while a second etch uses O2 applied in a single high power process at two successive different power levels. A first power level of between approximately 200 W and 500 W removes BARC, photoresist and Ta residue from the first etch, the second power level, between approximately 400 W and 600 W continues an etch of the stack layers and forms a protective oxide around the etched sides of the stack. Finally, an etch using a carbon, hydrogen and oxygen gas completes the etch while the oxide layer protects the cell from short-circuits across the lateral edges of the barrier layer.

Abstract translation: 通过使用Ta硬掩模层和蚀刻的组合，形成没有底脚并且穿过隧道势垒层的电短路的MTJ电池。 第一蚀刻图案Ta硬掩模，而第二蚀刻使用在两个连续的不同功率水平下在单个高功率过程中施加的O2。 在大约200W至500W之间的第一功率电平从第一蚀刻去除BARC，光致抗蚀剂和Ta残留物，第二功率电平在大约400W至600W之间，继续蚀刻叠层，并在其周围形成保护氧化物 蚀刻边的堆叠。 最后，使用碳，氢和氧气的蚀刻完成了蚀刻，而氧化物层保护电池免受横跨阻挡层的侧边缘的短路。

公开(公告)号：US20080225576A1

公开(公告)日：2008-09-18

申请号：US11724435

申请日：2007-03-15

Applicant: Tom Zhong ,  Terry Kin Ting Ko ,  Chyu-Jiuh Torng ,  Wai-Ming Kan ,  Adam Zhong

Inventor： Tom Zhong ,  Terry Kin Ting Ko ,  Chyu-Jiuh Torng ,  Wai-Ming Kan ,  Adam Zhong

IPC: G11C11/00

CPC classification number: H01L27/222 ,  H01L43/12 ,  Y10S977/935

Abstract: An MTJ pattern layout for a memory device is disclosed that includes two CMP assist features outside active MTJ device blocks. A first plurality of dummy MTJ devices is located in two dummy bands formed around an active MTJ device block. The inner dummy band is separated from the outer dummy band by the MTJ ILD layer and has a MTJ device density essentially the same as the MTJ device block. The outer dummy band has a MTJ device density at least 10% greater than the inner dummy band. The inner dummy band serves to minimize CMP edge effect in the MTJ device block while the outer dummy band improves planarization. A second plurality of dummy MTJ devices is employed in contact pads outside the outer dummy band and is formed between a WL ILD layer and a BIT ILD layer thereby minimizing delamination of the MTJ ILD layer.

Abstract translation: 公开了一种用于存储器件的MTJ图案布局，其包括主动MTJ器件块之外的两个CMP辅助特征。 第一组多个虚拟MTJ设备位于形成在活动MTJ设备块周围的两个虚拟带中。 内部虚拟带通过MTJ ILD层与外部虚拟带分离，并且具有与MTJ器件块基本相同的MTJ器件密度。 外虚拟带具有比内虚拟带大至少10％的MTJ装置密度。 内部虚拟带用于最小化MTJ器件块中的CMP边缘效应，而外部虚拟带改善了平坦化。 在外虚拟带外部的接触焊盘中采用第二多个虚拟MTJ器件，并且形成在WL ILD层和BIT ILD层之间，从而最小化MTJ ILD层的分层。