公开(公告)号：US20140061827A1

公开(公告)日：2014-03-06

申请号：US13597465

申请日：2012-08-29

Applicant: Kenlin Huang ,  Yuan-Tung Chin ,  Tom Zhong ,  Chyu-Jiuh Torng

Inventor： Kenlin Huang ,  Yuan-Tung Chin ,  Tom Zhong ,  Chyu-Jiuh Torng

IPC: H01L29/82 ,  H01L21/8239

CPC classification number: G01R33/098 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/308 ,  H01F41/325 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic thin film deposition is patterned and protected from oxidation during subsequent processes, such as bit line formation, by an oxidation-prevention encapsulation layer of SiN. The SiN layer is then itself protected during the processing by a metal overlayer, preferably of Ta, Al, TiN, TaN or W. A sequence of low pressure plasma etches, using Oxygen, Cl2, BCl3 and C2H4 chemistries provide selectivity of the metal overlayer to various oxide layers and to the photo-resist hard masks used in patterning and metal layer and thereby allow the formation of bit lines while maintaining the integrity of the SiN layer.

Abstract translation: 通过SiN的防氧化封装层，在随后的工艺（例如位线形成）中图案化和保护磁性薄膜沉积物免于氧化。 然后，SiN层在金属覆盖层，优选Ta，Al，TiN，TaN或W的加工过程中自身受到保护。使用氧气，Cl2，BCl3和C2H4化学物质的低压等离子体蚀刻序列提供金属覆层的选择性 到各种氧化物层和用于图案化和金属层中的光刻胶硬掩模，从而允许形成位线，同时保持SiN层的完整性。

公开(公告)号：US20130302912A1

公开(公告)日：2013-11-14

申请号：US13469258

申请日：2012-05-11

Applicant: Tom Zhong ,  Kenlin Huang ,  Chyu-Jiuh Torng

Inventor： Tom Zhong ,  Kenlin Huang ,  Chyu-Jiuh Torng

IPC: H01L21/02

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A method of forming a thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate so that the thin-film deposition is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer is formed on the CMOS substrate and is patterned by either forming undercut trenches extending into its upper surface or by fabricating T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage.

Abstract translation: 在晶片级CMOS衬底上形成诸如MTJ（磁性隧道结）层的薄膜沉积的方法，使得薄膜沉积被壁或沟槽分段，并且不受薄膜应力的影响 晶圆翘曲或其他后续退火工艺。 在CMOS衬底上形成界面层，并且通过形成延伸到其上表面的底切沟槽或通过制造沿其上表面延伸的T形壁而被图案化。 薄膜连续地沉积在图案化表面上，于是沟槽或壁分隔沉积物并用作应力消除机制，以消除作为诸如由晶片翘曲引起的应力的加工的不利影响。

公开(公告)号：US07408212B1

公开(公告)日：2008-08-05

申请号：US10777560

申请日：2004-02-11

Applicant: Harry S. Luan ,  Jein-Chen Young ,  Arthur Wang ,  Kai-Cheng Chou ,  Kenlin Huang

Inventor： Harry S. Luan ,  Jein-Chen Young ,  Arthur Wang ,  Kai-Cheng Chou ,  Kenlin Huang

IPC: H01L29/76

CPC classification number: G11C13/0007 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

Abstract: An electrically programmable, non-volatile resistive memory includes an array of memory cells, a plurality of bit lines, and a plurality of word lines. Each memory cell comprises a resistive element and a Schottky diode coupled in series and having first and second terminals. Each bit line couples to the first terminal of all memory cells in a respective column of the array. Each word line couples to the second terminal of all memory cells in a respective row of the array. The resistive element for each memory cell may be formed with a film of a perovskite material (e.g., Pr0.7Ca0.3MnO3). The Schottky diode for each memory cell may be formed by a thin film of amorphous silicon. The films for the resistive element and Schottky diode for each memory cell may be stacked in a compact island at the cross point between a bit line and a word line.

Abstract translation: 电可编程的非易失性电阻存储器包括存储器单元阵列，多个位线和多个字线。 每个存储单元包括串联耦合并具有第一和第二端子的电阻元件和肖特基二极管。 每个位线耦合到阵列的相应列中的所有存储器单元的第一端。 每个字线耦合到阵列的相应行中的所有存储器单元的第二端子。 用于每个存储单元的电阻元件可以由钙钛矿材料（例如，Pr 0.7 N 0.3 Mn 0.3 O 3）的膜形成。 每个存储单元的肖特基二极管可以由非晶硅薄膜形成。 用于每个存储单元的电阻元件和肖特基二极管的膜可以堆叠在位线和字线之间的交叉点处的紧凑岛中。

公开(公告)号：US07172939B1

公开(公告)日：2007-02-06

申请号：US11280529

申请日：2005-11-15

Applicant: Kai Cheng Chou ,  Harry Laun ,  Kenlin Huang ,  J. C. Young ,  Arthur Wang

Inventor： Kai Cheng Chou ,  Harry Laun ,  Kenlin Huang ,  J. C. Young ,  Arthur Wang

IPC: H01L21/336

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573

Abstract: An MONOS integrated circuit device. The device has a semiconductor substrate comprising a silicon bearing material and a shallow trench isolation region formed within the substrate. A P-type well region is formed within the substrate and adjacent to the shallow trench isolation region. The first word gate comprising a first edge and a second edge. The first word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. Preferably, the second word gate comprises a first edge and a second edge. The second word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. A common buried bit line is formed within the P-type well region and between the second edge of the first word gate and the first edge of the second word gate. An HDP plasma dielectric is formed overlying the common buried bitline to a height within a vicinity of a first surface of the first word gate and a second surface of the second word gate. In a preferred embodiment, the device has a planarized surface formed from a portion of the HDP plasma dielectric, the first surface, and the second surface. A word line is overlying the planarized surface. The word line is coupled to the first word gate and the second word gate and is overlying the HDP plasma dielectric. The device has a refractory metal layer formed overlying the word line, a hard mask layer overlying the refractory metal layer, and a cap layer formed overlying the hard mask layer. The word line, refractory metal layer, hard mask layer, and cap layer form a planarized structure.

Abstract translation: MONOS集成电路器件。 该器件具有包括硅衬底材料和形成在衬底内的浅沟槽隔离区域的半导体衬底。 P型阱区形成在衬底内并与浅沟槽隔离区相邻。 所述第一字门包括第一边缘和第二边缘。 第一字门包括耦合到第一边缘的第一控制栅极和耦合到第二边缘的第二控制栅极。 优选地，第二字门包括第一边缘和第二边缘。 第二字门包括耦合到第一边缘的第一控制栅极和耦合到第二边缘的第二控制栅极。 在P型阱区域内和第一字栅极的第二边缘与第二字门的第一边缘之间形成公共掩埋位线。 HDP等离子体电介质形成在公共掩埋位线上方至第一字栅极的第一表面附近的高度和第二字门的第二表面。 在优选实施例中，该装置具有由HDP等离子体电介质，第一表面和第二表面的一部分形成的平坦化表面。 字线覆盖在平坦化表面上。 字线耦合到第一字门和第二字门，并且覆盖HDP等离子体电介质。 该装置具有形成在字线上方的难熔金属层，覆盖难熔金属层的硬掩模层和覆盖在硬掩模层上的盖层。 字线，难熔金属层，硬掩模层和盖层形成平坦化结构。

公开(公告)号：US20050260857A1

公开(公告)日：2005-11-24

申请号：US10854755

申请日：2004-05-24

Applicant: Kenlin Huang ,  K.C. Chou ,  Harry Luan ,  J.C. Young ,  Arthur Wang

Inventor： Kenlin Huang ,  K.C. Chou ,  Harry Luan ,  J.C. Young ,  Arthur Wang

IPC: H01L21/302 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L45/04 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1675

Abstract: A high selectivity and etch rate with innovative approach of inductively coupled plasma source. Preferably, the invention includes a method using plasma chemistry that is divided into main etch step of (e.g., Cl2+HBr+C4F8) gas combination and over etch step of (e.g., HBr+Ar). The main etch step provides a faster etch rate and selectivity while the over etch step will decrease the etch rate and ensure the stringer and residue removal without attacking the under layer.

Abstract translation: 电感耦合等离子体源的创新方法具有高选择性和蚀刻速率。 优选地，本发明包括使用等离子体化学的方法，该方法被分为主蚀刻步骤（例如，Cl 2→H + HBr + C→S→S + ））（例如，HBr + Ar）的气体组合和过蚀刻步骤。 主蚀刻步骤提供更快的蚀刻速率和选择性，而过蚀刻步骤将降低蚀刻速率并确保桁条和残留物的去除而不侵蚀底层。

公开(公告)号：US20070126052A1

公开(公告)日：2007-06-07

申请号：US11292941

申请日：2005-12-01

Applicant: Harry Luan ,  J.C. Young ,  Arthur Wang ,  K.C. Chou ,  Kenlin Huang

Inventor： Harry Luan ,  J.C. Young ,  Arthur Wang ,  K.C. Chou ,  Kenlin Huang

IPC: H01L29/792

CPC classification number: H01L27/115 ,  H01L27/11519 ,  H01L27/11568

Abstract: A method of manufacturing a non-volatile semiconductor memory. The method includes forming a word gate poly layer on a substrate, wherein an upper surface of the substrate defines a plane of the substrate. The method also includes forming a first dielectric layer coupled to the word gate poly layer and patterning the word gate poly layer and the first dielectric layer to form an array of word gate structures. The method further includes forming a poly plug layer and patterning the poly plug layer to form a plurality of poly plugs surrounded in the plane of the substrate on three sides, forming a plurality of control gates, forming a second dielectric layer, planarizing the second dielectric layer using a chemical-mechanical polishing process, and depositing a metal layer to provide electrical contact to the word gate structures.

Abstract translation: 一种制造非易失性半导体存储器的方法。 该方法包括在衬底上形成字门多晶层，其中衬底的上表面限定衬底的平面。 该方法还包括形成耦合到字门多晶层的第一介电层，并且对门字多晶层和第一介电层进行构图以形成字门结构的阵列。 该方法还包括形成多晶硅塞层并构图多晶硅塞层以形成多个在三面的基片的平面中包围的多晶硅塞，形成多个控制栅极，形成第二介电层，平面化第二电介质 层，并且沉积金属层以提供与字栅结构的电接触。

公开(公告)号：US07186658B2

公开(公告)日：2007-03-06

申请号：US10854755

申请日：2004-05-24

Applicant: Kenlin Huang ,  Kaicheng Chou ,  Harry Luan ,  Jein-Chen Young ,  Arthur Wang

Inventor： Kenlin Huang ,  Kaicheng Chou ,  Harry Luan ,  Jein-Chen Young ,  Arthur Wang

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L45/04 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1675

Abstract: A high selectivity and etch rate with innovative approach of inductively coupled plasma source. Preferably, the invention includes a method using plasma chemistry that is divided into main etch step of (e.g., Cl2+HBr+C4F8) gas combination and over etch step of (e.g., HBr+Ar). The main etch step provides a faster etch rate and selectivity while the over etch step will decrease the etch rate and ensure the stringer and residue removal without attacking the under layer.

Abstract translation: 电感耦合等离子体源的创新方法具有高选择性和蚀刻速率。 优选地，本发明包括使用等离子体化学的方法，该方法被分为主蚀刻步骤（例如，Cl 2→H + HBr + C→S→S + ））（例如，HBr + Ar）的气体组合和过蚀刻步骤。 主蚀刻步骤提供更快的蚀刻速率和选择性，而过蚀刻步骤将降低蚀刻速率并确保桁条和残留物的去除而不侵蚀底层。

公开(公告)号：US08803293B2

公开(公告)日：2014-08-12

申请号：US13469258

申请日：2012-05-11

Applicant: Tom Zhong ,  Kenlin Huang ,  Chyu-Jiuh Torng

Inventor： Tom Zhong ,  Kenlin Huang ,  Chyu-Jiuh Torng

IPC: H01L29/06

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A method of forming a thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate so that the thin-film deposition is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer is formed on the CMOS substrate and is patterned by either forming undercut trenches extending into its upper surface or by fabricating T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage.

Abstract translation: 在晶片级CMOS衬底上形成诸如MTJ（磁性隧道结）层的薄膜沉积的方法，使得薄膜沉积被壁或沟槽分段，并且不受薄膜应力的影响 晶圆翘曲或其他后续退火工艺。 在CMOS衬底上形成界面层，并且通过形成延伸到其上表面的底切沟槽或通过制造沿其上表面延伸的T形壁而被图案化。 薄膜连续地沉积在图案化表面上，于是沟槽或壁分隔沉积物并用作应力消除机制，以消除作为诸如由晶片翘曲引起的应力的加工的不利影响。

公开(公告)号：US20070026606A1

公开(公告)日：2007-02-01

申请号：US11280529

申请日：2005-11-15

Applicant: Kai Chou ,  Harry Laun ,  Kenlin Huang ,  J.C. Young ,  Arthur Wang

Inventor： Kai Chou ,  Harry Laun ,  Kenlin Huang ,  J.C. Young ,  Arthur Wang

IPC: H01L21/336

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573

Abstract: An MONOS integrated circuit device. The device has a semiconductor substrate comprising a silicon bearing material and a shallow trench isolation region formed within the substrate. A P-type well region is formed within the substrate and adjacent to the shallow trench isolation region. The first word gate comprising a first edge and a second edge. The first word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. Preferably, the second word gate comprises a first edge and a second edge. The second word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. A common buried bit line is formed within the P-type well region and between the second edge of the first word gate and the first edge of the second word gate. An HDP plasma dielectric is formed overlying the common buried bitline to a height within a vicinity of a first surface of the first word gate and a second surface of the second word gate. In a preferred embodiment, the device has a planarized surface formed from a portion of the HDP plasma dielectric, the first surface, and the second surface. A word line is overlying the planarized surface. The word line is coupled to the first word gate and the second word gate and is overlying the HDP plasma dielectric. The device has a refractory metal layer formed overlying the word line, a hard mask layer overlying the refractory metal layer, and a cap layer formed overlying the hard mask layer. The word line, refractory metal layer, hard mask layer, and cap layer form a planarized structure.

Abstract translation: MONOS集成电路器件。 该器件具有包括硅衬底材料和形成在衬底内的浅沟槽隔离区域的半导体衬底。 P型阱区形成在衬底内并与浅沟槽隔离区相邻。 所述第一字门包括第一边缘和第二边缘。 第一字门包括耦合到第一边缘的第一控制栅极和耦合到第二边缘的第二控制栅极。 优选地，第二字门包括第一边缘和第二边缘。 第二字门包括耦合到第一边缘的第一控制栅极和耦合到第二边缘的第二控制栅极。 在P型阱区域内和第一字栅极的第二边缘与第二字门的第一边缘之间形成公共掩埋位线。 HDP等离子体电介质形成在公共掩埋位线上方至第一字栅极的第一表面附近的高度和第二字门的第二表面。 在优选实施例中，该装置具有由HDP等离子体电介质，第一表面和第二表面的一部分形成的平坦化表面。 字线覆盖在平坦化表面上。 字线耦合到第一字门和第二字门，并且覆盖HDP等离子体电介质。 该装置具有形成在字线上方的难熔金属层，覆盖难熔金属层的硬掩模层和覆盖在硬掩模层上的盖层。 字线，难熔金属层，硬掩模层和盖层形成平坦化结构。

公开(公告)号：US06638874B2

公开(公告)日：2003-10-28

申请号：US10198298

申请日：2002-07-17

Applicant: Sang In Yi ,  Seowoo Nam ,  Kenlin Huang ,  Padmapani C. Nallan

Inventor： Sang In Yi ,  Seowoo Nam ,  Kenlin Huang ,  Padmapani C. Nallan

IPC: H01L21302

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/32136

Abstract: One embodiment of the present invention is a method used to fabricate a device on a substrate, which method is utilized at a stage of processing wherein a metal gate stack is disposed or formed over a gate oxide, which metal stack includes a refractory metal layer disposed or formed over a refractory metal barrier/adhesion layer, which method includes steps of: (a) etching the refractory metal layer and stopping on or in the refractory metal barrier/adhesion layer; and (b) etching the refractory metal barrier/adhesion layer using a passivation etching chemistry without oxygen.

Abstract translation: 本发明的一个实施方案是用于在衬底上制造器件的方法，该方法在处理阶段被利用，其中在栅极氧化物上设置或形成金属栅极堆叠，该金属堆叠包括设置的难熔金属层 或形成在难熔金属阻挡层/粘合层上，该方法包括以下步骤：（a）蚀刻难熔金属层并停留在难熔金属屏障/粘合层上或其中; 和（b）使用无氧的钝化蚀刻化学蚀刻难熔金属阻挡层/粘附层。