公开(公告)号：US08288219B2

公开(公告)日：2012-10-16

申请号：US12052374

申请日：2008-03-20

Applicant: Peter Rabkin ,  Hsingya Arthur Wang ,  Kai-Cheng Chou

Inventor： Peter Rabkin ,  Hsingya Arthur Wang ,  Kai-Cheng Chou

IPC: H01L21/8238

CPC classification number: H01L27/11526 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/42324

Abstract: A stack of two polysilicon layers is formed over a semiconductor body region. A DDD implant is performed to form a DDD source region in the semiconductor body region along a source side of the polysilicon stack but not along a drain side of the polysilicon stack. Off-set spacers are formed along opposing side-walls of the polysilicon stack. A source/drain implant is performed to form a drain region in the semiconductor body region along the drain side of the polysilicon stack and to form a highly doped region within the DDD source region such that the extent of an overlap between the polysilicon stack and each of the drain region and the highly doped region is inversely dependent on a thickness of the off-set spacers, and a lateral spacing directly under the polysilicon stack between adjacent edges of the DDD source region and the highly doped region is directly dependent on the thickness of the off-set spacers.

Abstract translation: 在半导体主体区域上形成一叠两层多晶硅层。 执行DDD注入以在半导体主体区域中沿着多晶硅堆叠的源极侧形成DDD源极区域，但不沿着多晶硅叠层的漏极侧。 偏移间隔物沿着多晶硅堆叠的相对侧壁形成。 进行源极/漏极注入以沿着多晶硅堆叠的漏极侧在半导体主体区域中形成漏极区域，并且在DDD源极区域内形成高度掺杂的区域，使得多晶硅堆叠和每个 漏极区域和高掺杂区域的反向取决于偏置间隔物的厚度，并且在DDD源极区域和高度掺杂区域的相邻边缘之间直接在多晶硅堆叠下面的横向间隔直接取决于厚度 的偏置间隔物。

公开(公告)号：US07202134B2

公开(公告)日：2007-04-10

申请号：US11022005

申请日：2004-12-21

Applicant: Peter Rabkin ,  Hsingya Arthur Wang ,  Kai-Cheng Chou

Inventor： Peter Rabkin ,  Hsingya Arthur Wang ,  Kai-Cheng Chou

IPC: H01L21/336

CPC classification number: H01L27/11526 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/42324

Abstract: A gate electrode is formed over but insulated from a semiconductor body region for each of first and second transistors. A DDD implant is carried out to from DDD source and DDD drain regions in the body region for the first transistor. After the DDD implant, off-set spacers are formed along side-walls of the gate electrode of each of the first and second transistors. After forming the off-set spacers, a LDD implant is carried out to from LDD source and drain regions in the body region for the second transistor. After the LDD implant, main spacers are formed adjacent the off-set spacers of at least the second transistor. After forming the main spacers, a source/drain implant is carried out to form a highly doped region within each of the DDD drain and source regions and the LDD drain and source regions.

Abstract translation: 对于第一和第二晶体管中的每一个，栅电极形成在半导体本体区域的绝缘上。 从DDD源和DDD漏极区域对第一晶体管进行DDD注入。 在DDD植入之后，沿着第一和第二晶体管的每一个的栅电极的侧壁形成偏置间隔物。 在形成偏置间隔物之后，从第二晶体管的体区中的LDD源极和漏极区域执行LDD注入。 在LDD注入之后，主间隔物形成在至少第二晶体管的偏置间隔物附近。 在形成主间隔物之后，进行源极/漏极注入以在每个DDD漏极和源极区域以及LDD漏极和源极区域内形成高掺杂区域。

公开(公告)号：US20050186739A1

公开(公告)日：2005-08-25

申请号：US11100123

申请日：2005-04-05

Applicant: Hsingya Arthur Wang ,  Kai-Cheng Chou ,  Peter Rabkin

Inventor： Hsingya Arthur Wang ,  Kai-Cheng Chou ,  Peter Rabkin

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A non-volatile memory device includes a substrate having a first active region and a second active region. A first floating gate is provided over the first active region and having an edge, the first floating gate being made of a conductive material. A first spacer is connected to the edge of the first floating gate and being made of the same conductive material as that of the first floating gate. A control gate is provided proximate to the floating gate.

公开(公告)号：US06876582B2

公开(公告)日：2005-04-05

申请号：US10431165

申请日：2003-05-06

Applicant: Hsingya A. Wang ,  Kai-Cheng Chou ,  Peter Rabkin

Inventor： Hsingya A. Wang ,  Kai-Cheng Chou ,  Peter Rabkin

IPC: G11C16/02 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/00

CPC classification number: G11C16/16

Abstract: A method of erasing a non-volatile memory includes applying a first potential of first polarity to a control gate; applying a second potential of second polarity to a bulk region, the second potential being an N magnitude; and applying a third potential of second polarity to a source region, the third potential being an M magnitude, wherein the N and M are substantially the same.

Abstract translation: 擦除非易失性存储器的方法包括将第一极性的第一电位施加到控制栅极; 将第二极性的第二电位施加到体区，所述第二电位为N幅度; 以及向源极区施加第二极性的第三电位，所述第三电位为M幅度，其中所述N和M基本上相同。

公开(公告)号：US06746906B2

公开(公告)日：2004-06-08

申请号：US09808097

申请日：2001-03-13

Applicant: Peter Rabkin ,  Hsingya Arthur Wang ,  Kai-Cheng Chou

Inventor： Peter Rabkin ,  Hsingya Arthur Wang ,  Kai-Cheng Chou

IPC: H01L21265

CPC classification number: H01L27/11526 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/42324

Abstract: In one embodiment of the present invention, a method of forming semiconductor transistors includes: forming a gate electrode over but insulated from a semiconductor body region; forming off-set spacers along side-walls of the gate electrode; and after forming said off-set spacers, forming a source region and a drain region in the body region so that the extent of an overlap between the gate electrode and each of the source and drain regions is dependent on a thickness of the off-set spacers. In another embodiment, a method of forming a non-volatile memory cell includes: forming a first polysilicon layer over but insulated from a semiconductor body region; forming a second polysilicon layer over but insulated from the first polysilicon layer; forming an off-set spacer along at least one side-wall of the first and second polysilicon layers; and after forming said off-set spacer, forming at least one of source and drain regions in the body region so that the extent of an overlap between the first polysilicon layer and said one of source and drain regions is dependent on a thickness of the off-set spacer.

Abstract translation: 在本发明的一个实施例中，形成半导体晶体管的方法包括：在半导体本体区域上形成绝缘的栅电极; 沿着栅电极的侧壁形成偏置间隔物; 并且在形成所述偏置间隔物之后，在体区域中形成源极区域和漏极区域，使得栅极电极和源极区域和漏极区域中的每一个之间的重叠程度取决于偏移的厚度 间隔物 在另一个实施例中，形成非易失性存储单元的方法包括：在半导体本体区域之上形成绝缘的第一多晶硅层; 在第一多晶硅层上形成第二多晶硅层，但与第一多晶硅层绝缘; 沿着所述第一和第二多晶硅层的至少一个侧壁形成偏置间隔物; 并且在形成所述偏置间隔物之后，在体区中形成源区和漏区中的至少一个，使得第一多晶硅层与所述源极和漏极区之间的重叠程度取决于关闭的厚度 设置间隔。

公开(公告)号：US07160774B2

公开(公告)日：2007-01-09

申请号：US10870285

申请日：2004-06-16

Applicant: Peter Rabkin ,  Hsingya Arthur Wang ,  Kai-Cheng Chou

Inventor： Peter Rabkin ,  Hsingya Arthur Wang ,  Kai-Cheng Chou

IPC: H01L21/336

CPC classification number: H01L29/4916 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7883

Abstract: In accordance with an embodiment of the present invention, a semiconductor structure includes an undoped polysilicon layer, a doped polysilicon layer in contact with the undoped polysilicon layer, and an insulating layer in contact with the undoped polysilicon layer. The undoped polysilicon layer is sandwiched between the doped polysilicon layer and the insulating layer.

Abstract translation: 根据本发明的实施例，半导体结构包括未掺杂多晶硅层，与未掺杂多晶硅层接触的掺杂多晶硅层，以及与未掺杂多晶硅层接触的绝缘层。 未掺杂的多晶硅层夹在掺杂多晶硅层和绝缘层之间。

公开(公告)号：US20060252193A1

公开(公告)日：2006-11-09

申请号：US11487093

申请日：2006-07-13

Applicant: Peter Rabkin ,  Hsingya Wang ,  Kai-Cheng Chou

Inventor： Peter Rabkin ,  Hsingya Wang ,  Kai-Cheng Chou

IPC: H01L21/336 ,  H01L21/22

CPC classification number: H01L29/4916 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/7883

Abstract: A semiconductor transistor which is not capable of storing data is formed as follows. An insulating layer is formed over a silicon region. An undoped polysilicon layer is formed over and in contact with the insulating layer. A doped polysilicon layer is formed over and in contact with the undoped polysilicon layer such that at least two edges of the doped polysilicon layer vertically line up with corresponding edges of the undoped polysilicon layer to thereby form sidewalls, and the doped and undoped polysilicon layers form a gate of the transistor. After the doped polysilicon layer is formed, source and drain regions are formed in the silicon region. Dopants from the doped polysilicon layer migrate into the undoped polysilicon layer thereby doping the undoped polysilicon layer.

Abstract translation: 如下形成不能存储数据的半导体晶体管。 在硅区域上形成绝缘层。 在绝缘层上形成未掺杂的多晶硅层，并与绝缘层接触。 掺杂多晶硅层形成在未掺杂的多晶硅层之上并与未掺杂的多晶硅层接触，使得掺杂多晶硅层的至少两个边缘与未掺杂的多晶硅层的相应边缘垂直地对齐，从而形成侧壁，并且掺杂和未掺杂的多晶硅层形成 晶体管的栅极。 在形成掺杂多晶硅层之后，在硅区域中形成源区和漏区。 来自掺杂多晶硅层的掺杂剂迁移到未掺杂的多晶硅层中，从而掺杂未掺杂的多晶硅层。

公开(公告)号：US06812515B2

公开(公告)日：2004-11-02

申请号：US09994545

申请日：2001-11-26

Applicant: Peter Rabkin ,  Hsingya Arthur Wang ,  Kai-Cheng Chou

Inventor： Peter Rabkin ,  Hsingya Arthur Wang ,  Kai-Cheng Chou

IPC: H01L29788

CPC classification number: H01L29/4916 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7883

Abstract: A non-volatile memory cell includes a first insulating layer over a substrate region, and a floating gate. The floating gate includes a first polysilicon layer over the first insulating layer and a second polysilicon layer over and in contact with the first polysilicon layer. The first polysilicon layer has a predetermined doping concentration and the second polysilicon layer has a doping concentration which decreases in a direction away from an interface between the first and second polysilicon layers. A second insulating layer overlies and is in contact with the second polysilicon layer. A control gate includes a third polysilicon layer over and in contact with the second insulating layer, and a fourth polysilicon layer over and in contact with the third polysilicon layer. The fourth polysilicon layer has a predetermined doping concentration, and the third polysilicon layer has a doping concentration which decreases in a direction away from an interface between the third and fourth polysilicon layers.

Abstract translation: 非易失性存储单元包括在衬底区域上的第一绝缘层和浮置栅极。 浮置栅极包括在第一绝缘层之上的第一多晶硅层和在第一多晶硅层上并与第一多晶硅层接触的第二多晶硅层。 第一多晶硅层具有预定的掺杂浓度，并且第二多晶硅层具有在远离第一和第二多晶硅层之间的界面的方向上减小的掺杂浓度。 第二绝缘层覆盖并与第二多晶硅层接触。 控制栅极包括在第二绝缘层上并与第二绝缘层接触的第三多晶硅层，以及在第三多晶硅层上并与第三多晶硅层接触的第四多晶硅层。 第四多晶硅层具有预定的掺杂浓度，并且第三多晶硅层具有在远离第三和第四多晶硅层之间的界面的方向上减小的掺杂浓度。

公开(公告)号：US06559008B2

公开(公告)日：2003-05-06

申请号：US09971434

申请日：2001-10-04

Applicant: Peter Rabkin ,  Hsingya Arthur Wang ,  Kai-Cheng Chou

Inventor： Peter Rabkin ,  Hsingya Arthur Wang ,  Kai-Cheng Chou

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.

公开(公告)号：US08946003B2

公开(公告)日：2015-02-03

申请号：US11676777

申请日：2007-02-20

Applicant: Peter Rabkin ,  Hsingya Arthur Wang ,  Kai-Cheng Chou

Inventor： Peter Rabkin ,  Hsingya Arthur Wang ,  Kai-Cheng Chou

IPC: H01L21/8232 ,  H01L21/8234 ,  H01L27/115 ,  H01L27/105 ,  H01L29/423

CPC classification number: H01L27/11526 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/42324

Abstract: A semiconductor transistor is formed as follows. A gate electrode is formed over but is insulated from a semiconductor body region. A first layer of insulating material is formed over the gate electrode and the semiconductor body region. A second layer of insulating material different from the first layer of insulating material is formed over the first layer of insulating material. Only the second layer of insulating material is etched to form spacers along the side-walls of the gate electrode. Impurities are implanted through the first layer of insulating material to form a source region and a drain region in the body region. A substantial portion of those portions of the first layer of insulting material extending over the source and drain regions is removed.

Abstract translation: 如下形成半导体晶体管。 栅电极形成在半导体本体区域上而与半导体本体区域绝缘​​。 第一层绝缘材料形成在栅电极和半导体本体区域上。 与第一绝缘材料层不同的第二绝缘材料层形成在第一绝缘材料层上。 仅蚀刻绝缘材料的第二层，沿着栅电极的侧壁形成间隔物。 通过第一绝缘材料层注入杂质以在体区域中形成源极区域和漏极区域。 去除在源区和漏区上延伸的第一层绝缘材料的那些部分的大部分。