公开(公告)号：US06693830B1

公开(公告)日：2004-02-17

申请号：US10011549

申请日：2001-10-22

Applicant: Yongzhong Hu ,  Jein-Chen Young

Inventor： Yongzhong Hu ,  Jein-Chen Young

IPC: G11C1604

CPC classification number: G11C16/0433 ,  G11C16/0441 ,  G11C2216/10

Abstract: An EEPROM cell includes a sense transistor and a select transistor, each having a first active region (110, 114) formed in a substrate, and sharing a second active region (112). The EEPROM cell may also include a floating gate (125) having a first portion (FG2) forming a gate region for said sense transistor, and a second portion (FG1) overlying the second active region and forming a program junction with said second active region. The first portion of said floating gate has a concentration of an impurity greater than a concentration of said impurity in the second portion of the floating gate.

Abstract translation: EEPROM单元包括检测晶体管和选择晶体管，每个具有形成在衬底中的第一有源区（110,114），并且共享第二有源区（112）。 EEPROM单元还可以包括具有形成用于所述读出晶体管的栅极区域的第一部分（FG2）的浮动栅极（125）和覆盖第二有源区域并与第二有源区域形成程序结的第二部分（FG1） 。 所述浮置栅极的第一部分具有大于浮动栅极的第二部分中所述杂质浓度的杂质浓度。

公开(公告)号：US5866467A

公开(公告)日：1999-02-02

申请号：US886844

申请日：1997-07-01

Applicant: Hsingya Arthur Wang ,  Jein-Chen Young ,  Nicholas H. Tripsas

Inventor： Hsingya Arthur Wang ,  Jein-Chen Young ,  Nicholas H. Tripsas

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76205 ,  H01L21/7621

Abstract: A silicon substrate has patterned thereon a pad oxide layer and a nitride layer. The exposed surface of the silicon substrate is cleaned of residual oxide, and a layer of oxidizable material such as polysilicon is deposit over the resulting structure. The polysilicon layer is anisotropically etched to form spacers on the side of the nitride layer portions, which are also in contact with the silicon substrate, the etching continuing into the silicon substrate. Field oxidation is then undertaken, with the polysilicon spacers being oxidized, as is a portion of the silicon substrate, the spacers causing initial oxidation during field oxide growth to be removed from the sides of the nitride layer portions, so that encroachment of the oxide under the nitride layer portions is avoided.

Abstract translation: 硅衬底上形成有衬垫氧化物层和氮化物层。 清除硅衬底的暴露表面残留的氧化物，并且在所得结构上沉积一层可氧化材料如多晶硅。 各向异性蚀刻多晶硅层，以在与硅衬底接触的氮化物层部分一侧形成间隔物，蚀刻继续进入硅衬底。 然后进行场氧化，其中多晶硅间隔物被氧化，如硅衬底的一部分，在场氧化物生长期间引起初始氧化的间隔物从氮化物层部分的侧面去除，使得氧化物侵蚀在 避免了氮化物层部分。

公开(公告)号：US06525970B2

公开(公告)日：2003-02-25

申请号：US09976232

申请日：2001-10-12

Applicant: Arthur Wang ,  Jein-Chen Young ,  Ming Kwan

Inventor： Arthur Wang ,  Jein-Chen Young ,  Ming Kwan

IPC: G11C1604

CPC classification number: H01L27/11526 ,  H01L27/115 ,  H01L27/11546

Abstract: A method of erasing electrically a programmable memory cell which cell includes a transistor formed in a region of semiconductor material. The transistor has a source region, a drain region, a floating gate, and a control gate. The method comprises lowering the control gate to a potential of about −9 volts, disconnecting the source and drain regions from any potential source, and placing the region of semiconductor material at a potential of about 9 volts.

Abstract translation: 一种擦除可编程存储器单元的方法，该单元包括形成在半导体材料区域中的晶体管。 晶体管具有源极区，漏极区，浮动栅极和控制栅极。 该方法包括将控制栅极降低到约-9伏特的电势，将源极和漏极区域从任何潜在源断开，并将半导体材料区域置于约9伏特的电位。

公开(公告)号：US07408212B1

公开(公告)日：2008-08-05

申请号：US10777560

申请日：2004-02-11

Applicant: Harry S. Luan ,  Jein-Chen Young ,  Arthur Wang ,  Kai-Cheng Chou ,  Kenlin Huang

Inventor： Harry S. Luan ,  Jein-Chen Young ,  Arthur Wang ,  Kai-Cheng Chou ,  Kenlin Huang

IPC: H01L29/76

CPC classification number: G11C13/0007 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

Abstract: An electrically programmable, non-volatile resistive memory includes an array of memory cells, a plurality of bit lines, and a plurality of word lines. Each memory cell comprises a resistive element and a Schottky diode coupled in series and having first and second terminals. Each bit line couples to the first terminal of all memory cells in a respective column of the array. Each word line couples to the second terminal of all memory cells in a respective row of the array. The resistive element for each memory cell may be formed with a film of a perovskite material (e.g., Pr0.7Ca0.3MnO3). The Schottky diode for each memory cell may be formed by a thin film of amorphous silicon. The films for the resistive element and Schottky diode for each memory cell may be stacked in a compact island at the cross point between a bit line and a word line.

Abstract translation: 电可编程的非易失性电阻存储器包括存储器单元阵列，多个位线和多个字线。 每个存储单元包括串联耦合并具有第一和第二端子的电阻元件和肖特基二极管。 每个位线耦合到阵列的相应列中的所有存储器单元的第一端。 每个字线耦合到阵列的相应行中的所有存储器单元的第二端子。 用于每个存储单元的电阻元件可以由钙钛矿材料（例如，Pr 0.7 N 0.3 Mn 0.3 O 3）的膜形成。 每个存储单元的肖特基二极管可以由非晶硅薄膜形成。 用于每个存储单元的电阻元件和肖特基二极管的膜可以堆叠在位线和字线之间的交叉点处的紧凑岛中。

公开(公告)号：US06366499B1

公开(公告)日：2002-04-02

申请号：US09689026

申请日：2000-10-10

Applicant: Arthur Arthur Wang ,  Jein-Chen Young ,  Ming Kwan

Inventor： Arthur Arthur Wang ,  Jein-Chen Young ,  Ming Kwan

IPC: G11C1604

CPC classification number: H01L27/11526 ,  H01L27/115 ,  H01L27/11546

Abstract: A method of programming an electrically programmable memory cell which cell includes a transistor formed in a semiconductor substrate of first conductivity type having a surface a first well region of second conductivity type is disposed in the substrate adjacent the surface thereof. A second well region of first conductivity type is disposed in the first well region adjacent the surface. The transistor has a source region, a drain region, a floating gate, and a control gate. The method includes raising the control gate to a first selected potential no greater than 9.0 volts, raising the drain to a potential to no more than 5.0 volts, coupling the source region to ground potential, coupling the first well region of second conductivity type to ground potential, and placing the second well region at a potential below ground potential.

Abstract translation: 一种编程电可编程存储单元的方法，该单元包括形成在具有第二导电类型的第一阱区的第一导电类型的半导体衬底中的晶体管的晶体管，邻近其表面。 第一导电类型的第二阱区域布置在邻近表面的第一阱区域中。 晶体管具有源极区，漏极区，浮动栅极和控制栅极。 该方法包括将控制栅极升高到不大于9.0伏特的第一选定电位，将漏极升高至不超过5.0伏的电位，将源极区域耦合到接地电位，将第二导电类型的第一阱区域耦合到地 电位，并将第二阱区域置于低于地电势的电位。

公开(公告)号：US6043123A

公开(公告)日：2000-03-28

申请号：US863917

申请日：1997-05-27

Applicant: Hsingya Arthur Wang ,  Jein-Chen Young ,  Ming-Sang Kwan

Inventor： Hsingya Arthur Wang ,  Jein-Chen Young ,  Ming-Sang Kwan

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L27/115 ,  H01L27/11546

Abstract: A process is described for fabricating an integrated circuit memory in a semiconductor substrate. In the substrate, a first well is formed by introduction of dopant opposite to conductivity of the substrate. Within the first well a second well is formed of conductivity type matching the substrate. The memory cells are fabricated in the second well and have source and drain regions opposite the conductivity type substrate. Each of the first and second wells also includes a region of corresponding conductivity type to enable separate electrical connections to be made to each of the wells.

Abstract translation: 描述了在半导体衬底中制造集成电路存储器的过程。 在衬底中，通过引入与衬底的导电性相反的掺杂剂形成第一阱。 在第一阱内，第二阱由与衬底相匹配的导电类型形成。 存储单元被制造在第二阱中并且具有与导电类型衬底相对的源区和漏区。 第一和第二孔中的每一个还包括相应导电类型的区域，以使得能够对每个孔进行单独的电连接。

公开(公告)号：US07186658B2

公开(公告)日：2007-03-06

申请号：US10854755

申请日：2004-05-24

Applicant: Kenlin Huang ,  Kaicheng Chou ,  Harry Luan ,  Jein-Chen Young ,  Arthur Wang

Inventor： Kenlin Huang ,  Kaicheng Chou ,  Harry Luan ,  Jein-Chen Young ,  Arthur Wang

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L45/04 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1675

Abstract: A high selectivity and etch rate with innovative approach of inductively coupled plasma source. Preferably, the invention includes a method using plasma chemistry that is divided into main etch step of (e.g., Cl2+HBr+C4F8) gas combination and over etch step of (e.g., HBr+Ar). The main etch step provides a faster etch rate and selectivity while the over etch step will decrease the etch rate and ensure the stringer and residue removal without attacking the under layer.

Abstract translation: 电感耦合等离子体源的创新方法具有高选择性和蚀刻速率。 优选地，本发明包括使用等离子体化学的方法，该方法被分为主蚀刻步骤（例如，Cl 2→H + HBr + C→S→S + ））（例如，HBr + Ar）的气体组合和过蚀刻步骤。 主蚀刻步骤提供更快的蚀刻速率和选择性，而过蚀刻步骤将降低蚀刻速率并确保桁条和残留物的去除而不侵蚀底层。

公开(公告)号：US06627947B1

公开(公告)日：2003-09-30

申请号：US09643279

申请日：2000-08-22

Applicant: Yongzhong Hu ,  Jein Chen Young ,  Stewart Logie

Inventor： Yongzhong Hu ,  Jein Chen Young ,  Stewart Logie

IPC: H01L29788

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L29/7885

Abstract: A non-volatile memory cell at least partially formed in a semiconductor substrate. The cell comprises a first transistor comprising a high voltage NMOS transistor having a first active region and a second active region; a second transistor sharing said second active region and having a third active region in said substrate; an active control gate region formed in said substrate; a polysilicon layer having a first portion forming a gate for said first transistor, and a second portion forming gate for said second transistor and a floating gate overlying said active control gate region. In one embodiment, an oxynitride separates said second portion and said active control gate region.

Abstract translation: 至少部分地形成在半导体衬底中的非易失性存储单元。 该单元包括第一晶体管，其包括具有第一有源区和第二有源区的高电压NMOS晶体管; 共享所述第二有源区并在所述衬底中具有第三有源区的第二晶体管; 形成在所述基板中的有源控制栅极区域; 多晶硅层，具有形成所述第一晶体管的栅极的第一部分，以及形成所述第二晶体管的栅极的第二部分和覆盖所述有源控制栅极区域的浮动栅极。 在一个实施例中，氧氮化物分离所述第二部分和所述主动控制栅极区域。

公开(公告)号：US5920506A

公开(公告)日：1999-07-06

申请号：US938389

申请日：1997-09-26

Applicant: Hsingya Arthur Wang ,  Haike Dong ,  Jein-Chen Young ,  Yuan Tang ,  Aaron Yip ,  Kenneth Miu

Inventor： Hsingya Arthur Wang ,  Haike Dong ,  Jein-Chen Young ,  Yuan Tang ,  Aaron Yip ,  Kenneth Miu

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/04

CPC classification number: G11C16/107 ,  G11C16/10 ,  G11C16/16 ,  G11C2216/16

Abstract: Apparatus is provided to facilitate the process of bulk preprogramming each of the cells in a flash memory or a subblock of a flash memory. In the process, the source and drain of each cell to be preprogrammed is biased such that current need not be flowing between the source and drain through the cell's channel region for charge to be transferred between the cell's channel region and the cell's floating gate. In a specific embodiment, the sources and drains are left floating without any particular bias voltage and the control gates of the cells are set to between 9 and 12 volts above the substrate and held there for about 10 milliseconds (ms). In an alternate embodiment, the sources and drains of all of the cells to be preprogrammed are biased to the same potential, which is a negative voltage, ground, or a positive voltage.

Abstract translation: 提供了设备以便于批量预编程闪速存储器或闪速存储器的子块中的每个单元的处理。 在该过程中，要预编程的每个单元的源极和漏极被偏置，使得电流不需要在源极和漏极之间通过电池的沟道区域流动，以在电池的沟道区域和电池的浮动栅极之间传输电荷。 在具体实施例中，源极和漏极在没有任何特定偏置电压的情况下保持浮置，并且单元的控制栅极被设置在衬底上方9到12伏之间并保持在大约10毫秒（ms）。 在替代实施例中，要预编程的所有单元的源极和漏极被偏置到相同的电位，其是负电压，接地或正电压。

公开(公告)号：US06347054B1

公开(公告)日：2002-02-12

申请号：US09496293

申请日：2000-02-01

Applicant: Arthur Arthur Wang ,  Jein-Chen Young ,  Ming-Sang Kwan

Inventor： Arthur Arthur Wang ,  Jein-Chen Young ,  Ming-Sang Kwan

IPC: G11C1604

CPC classification number: H01L27/11526 ,  H01L27/115 ,  H01L27/11546

Abstract: A method of erasing electrically a programmable memory cell which cell includes a transistor formed in a region of semiconductor material. The transistor has a source region, a drain region, a floating gate, and a control gate. The method includes lowering the control gate to a potential no more negative than 6.5 volts, disconnecting the source and drain regions from any potential source, and placing the region of semiconductor material at a potential no more positive than 8.0 volts.

Abstract translation: 一种擦除可编程存储器单元的方法，该单元包括形成在半导体材料区域中的晶体管。 晶体管具有源极区，漏极区，浮动栅极和控制栅极。 该方法包括将控制栅极降低至不超过6.5伏的电势，将源极和漏极区域从任何潜在源断开，并将半导体材料区域置于不超过8.0伏特的电位。