公开(公告)号：US20250054818A1

公开(公告)日：2025-02-13

申请号：US18930628

申请日：2024-10-29

Applicant: Sandisk Technologies, Inc.

Inventor： Akira Ogawa ,  Takashi Murai

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: An apparatus includes a semiconductor wafer including a first die and a second die, each including, a selector circuit including a first input terminal coupled to a first die bond pad, a second input terminal, and an output terminal, the selector circuit configured to selectively couple the first input terminal and the second input terminal to the output terminal, a conductor selectively configured to couple the second input terminal to either a first power supply or a second power supply, and an address determined based on a signal value at the output terminal of the selector circuit.

公开(公告)号：US20250004660A1

公开(公告)日：2025-01-02

申请号：US18230145

申请日：2023-08-03

Applicant: Sandisk Technologies, Inc.

Inventor： Daniel J. Linnen ,  Ramanathan Muthiah ,  Preston Thomson ,  Kirubakaran Periyannan ,  Niles Nian Yang ,  Inez Hua ,  Judah Gamliel Hahn

IPC: G06F3/06

Abstract: A process for reliably erasing data from a solid-state drive (SSD) includes first, prior to user data being stored on the drive, generating a restore image of information stored on the drive which characterizes a restore state of the drive, such as a factory image. Then, imparting energy to the drive to promote electrons representing bits in corresponding memory cells to exit the cells, such as imparting thermal energy or high-energy electromagnetic radiation to the drive. Also, generating a set of quantitative data for verifying erasure of the data for presentation to the user helps ensure trust in the data wipe process. The drive may also be electrically erased prior to imparting energy to the SSD, to provide another level of confidence in the data wipe process. The restore image may then be loaded to the necessary locations on the wiped drive to restore drive functionality.

公开(公告)号：US20240395328A1

公开(公告)日：2024-11-28

申请号：US18790609

申请日：2024-07-31

Applicant: Sandisk Technologies, Inc.

Inventor： Abhijith Prakash ,  Anubhav Khandelwal

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/32 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is configured to control a word line potential on the word line and a control gate potential on the control gate line and to control a state of the control gate. The memory controller circuit, when the nonvolatile memory transitions to a not-on state, is further configured to turn off the word line switch and to charge the control gate line to a charged potential.

公开(公告)号：US12114435B2

公开(公告)日：2024-10-08

申请号：US17744291

申请日：2022-05-13

Applicant: Sandisk Technologies, Inc.

Inventor： Virgil Zhu ,  Vincent Jiang ,  Paul Qu ,  Shixing Zhu ,  Yuanheng Zhang ,  Enoch He ,  Yonglong Liu ,  Lian Chen ,  Guangqiang Li ,  Jingyun Chen

IPC: B23K1/00 ,  B23K3/00 ,  B23K37/04 ,  H05K3/34 ,  B23K101/42

CPC classification number: H05K3/3494 ,  B23K1/0016 ,  B23K37/04 ,  H05K3/341 ,  H05K3/3457 ,  B23K2101/42

Abstract: A method of soldering one or more components to a substrate includes providing a substrate and applying an amount of solder material to the top planar surface of the substrate. One or more electrical components are mounted to the solder material in a predetermined position and orientation. A carrier is provided having one or more magnets embedded therein. The substrate is positioned above the carrier such that each of the one or more magnets is positioned directly below a corresponding electrical component. A carrier cover is positioned above the substrate and the electrical components. The solder material is heated to a predetermined temperature for a predetermined amount of time during which each of the magnets exerts a magnetic force on a corresponding electrical component to maintain its orientation relative to the substrate. The magnets reduce the occurrence of tombstoning of the electrical components during heating of the solder material.

公开(公告)号：US10223029B2

公开(公告)日：2019-03-05

申请号：US14977222

申请日：2015-12-21

Applicant: SanDisk Technologies Inc.

Inventor： Sergey Anatolievich Gorobets ,  Neil Richard Darragh ,  Liam Michael Parker

IPC: G06F3/06 ,  G11C16/28 ,  G11C16/32 ,  G06F11/07 ,  G11C16/34 ,  G11C29/52 ,  G11C11/56 ,  G11C16/12 ,  G11C29/02 ,  G06F11/00 ,  G11C29/50 ,  G11C29/00 ,  G11C29/56 ,  G11C16/04

Abstract: A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.

公开(公告)号：US10177128B2

公开(公告)日：2019-01-08

申请号：US14676628

申请日：2015-04-01

Applicant: SanDisk Technologies Inc.

Inventor： Chih Chin Liao ,  Sung Tan Shih ,  Suresh Kumar Upadhyayula ,  Ning Ye

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/498 ,  H01L21/48

Abstract: A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a substrate having a solder mask. A plurality of pillar bases are formed on the solder mask, and a plurality of solder pillars are applied to the pillar bases. The plurality of solder pillars support one or more semiconductor die above the substrate and the number of solder pillars prevent stresses in the one or more semiconductor die which could otherwise damage the semiconductor die.

公开(公告)号：US10134728B2

公开(公告)日：2018-11-20

申请号：US15087004

申请日：2016-03-31

Applicant: SanDisk Technologies Inc.

Inventor： Shiv Harit Mathur ,  Anand Sharma ,  Lakhdar Iguelmamene ,  Richard J K Hong ,  Rajeswara Rao Bandaru

IPC: H01L27/06 ,  H01L27/02

Abstract: An integrated circuit may include a plurality of input/output (I/O) cells used for communicating signals, power, and ground to and from a core of the integrated circuit. The I/O cells may each include a bond pad formed in one or more top metal layers. One or more of the bond pads may be offset a predetermined distance from an I/O cell edge corresponding to a chip edge of the integrated circuit. A volume may be determined by the I/O cell edge and the predetermined distance and one or more rails may be disposed in the volume and in at least one metal layer common with at least one metal layer of the bond pad. The rails may be involved in the discharge of electrostatic discharge (ESD) current, and may reduce path resistance of the path used to discharge the ESD current.

公开(公告)号：US10128261B2

公开(公告)日：2018-11-13

申请号：US14613956

申请日：2015-02-04

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Raghuveer S. Makala ,  Rahul Sharangpani ,  Sateesh Koka ,  Genta Mizuno ,  Naoki Takeguchi ,  Senaka Krishna Kanakamedala ,  George Matamis ,  Yao-Sheng Lee ,  Johann Alsmeier

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11563 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L21/3213 ,  H01L21/768 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11568

Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.

公开(公告)号：US10108470B2

公开(公告)日：2018-10-23

申请号：US14981386

申请日：2015-12-28

Applicant: SanDisk Technologies, Inc.

Inventor： Gulzar A. Kathawala ,  Shuenghee Park ,  Jingfeng Yuan ,  Mark Dancho

IPC: G06F11/00 ,  G06F11/07 ,  G06F12/00 ,  G06F11/10 ,  G11C29/00

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for parity storage management. A system includes a plurality of storage elements. A system includes a controller that selects a parity storage element from a plurality of storage elements. A parity storage element has an error rate higher than other elements of a plurality of storage elements, and the parity storage element stores parity data for the plurality of storage elements.

公开(公告)号：US10078614B2

公开(公告)日：2018-09-18

申请号：US14857136

申请日：2015-09-17

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Eliad Adi Klein ,  Rotem Sela ,  Miki Sapir

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4282 ,  G06F13/1668 ,  Y02D10/14 ,  Y02D10/151

Abstract: Data transfer between a data storage device and a peripheral device bypasses an application processor that is coupled to the data storage device and to the peripheral device. In one embodiment, the data storage device includes a memory controller configured to receive, from an application processor, a message indicating a set of logical addresses and a data transfer identifier corresponding to the set of logical addresses. The memory controller is responsive to a request for memory access that includes the data transfer identifier and that is received from a peripheral device. The memory controller is configured to respond to the request by performing a memory access operation based on the set of logical addresses.