摘要:
A solid state drive is disclosed including a planar array of semiconductor devices for use in a datacenter, and a system for cooling the planar array of semiconductor devices. The semiconductor devices may be arranged in a grid pattern, spaced apart from each other so as to define rows and columns of flow pathways, or cooling tunnels, around and between the semiconductor devices.
摘要:
The present technology relates to a semiconductor device. The semiconductor device comprises: a plurality of dies stacked on top of each other, each of the dies comprising a first major surface, an IO conductive pattern on the first major surface and extended to a minor surface substantially perpendicular to the major surfaces to form at least one IO electrical contact on the minor surface, and the plurality of dies aligned so that the corresponding minor surfaces of all dies substantially coplanar with respect to each other to form a common flat sidewall, and a plurality of IO routing traces formed over the sidewall and at least partially spaced away from the sidewall. The plurality of IO routing traces are spaced apart from each other in a first direction on the sidewall, and each of IO routing traces is electrically connected to a respective IO electrical contact and extended across the sidewall in a second direction substantially perpendicular to the first direction on the sidewall.
摘要:
A semiconductor device is disclosed including a stack of wafers having a densely configured 3D array of memory die. The memory die on each wafer may be arranged in clusters, with each cluster including an optical module providing an optical interconnection for the transfer of data to and from each cluster.
摘要:
A semiconductor device is disclosed mounted at an angle on a signal carrier medium such as a printed circuit board. The semiconductor device includes a stack of semiconductor die stacked in a stepped offset configuration. The die stack may then be encapsulated in a block of molding compound. The molding compound may then be singulated with slanted cuts along two opposed edges. The slanted edge may then be drilled to expose the electrical contacts on each of the semiconductor die. The slanted edge may then be positioned against a printed circuit board having solder or other conductive bumps so that the conductive bumps engage the semiconductor die electrical contacts in the drilled holes. The device may then be heated to reflow and connect the electrical contacts to the conductive bumps.
摘要:
A semiconductor device is disclosed including at least first and second vertically stacked and interconnected groups of semiconductor packages. The first and second groups of semiconductor packages may differ from each other in the number of packages and functionality.
摘要:
The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.
摘要:
A semiconductor device is disclosed including at least first and second vertically stacked and interconnected semiconductor packages. Signal communication between the second semiconductor package and a host device occurs through the first semiconductor package.
摘要:
A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die, mounted on a surface of a substrate. A bridge structure is also mounted to the substrate, with the semiconductor die fitting within a trench formed in a bottom surface of the bridge structure. The bridge structure may be formed from a semiconductor wafer into either a dummy bridge structure functioning as a mechanical spacer layer, or an IC bridge structure functioning as both a mechanical spacer layer and an integrated circuit semiconductor die. Memory die may also be mounted atop the bridge structure.
摘要:
A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations.
摘要:
The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.