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    Graphene growth on a non-hexagonal lattice
    1.
    发明授权
    Graphene growth on a non-hexagonal lattice 有权
    非六方晶格上的石墨烯生长

    公开(公告)号：US08877340B2

    公开(公告)日：2014-11-04

    申请号：US12844029

    申请日：2010-07-27

    申请人： Jack O. Chu ,  Christos Dimitrakopoulos ,  Marcus O. Freitag ,  Alfred Grill ,  Timothy J. McArdle ,  Chun-Yung Sung ,  Robert L. Wisnieff

    发明人： Jack O. Chu ,  Christos Dimitrakopoulos ,  Marcus O. Freitag ,  Alfred Grill ,  Timothy J. McArdle ,  Chun-Yung Sung ,  Robert L. Wisnieff

    IPC分类号： B32B9/00

    CPC分类号： H01L21/02527 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/188 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02516 ,  Y10T428/30

    摘要： A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry.

    摘要翻译： 在具有非六边形对称性的结晶表面上形成石墨烯层。 晶体表面可以是单晶半导体碳化物层的表面。 单晶半导体碳化物层的非六边形对称表面在超高真空环境中在升高的温度下退火以形成石墨烯层。 在退火过程中，单晶半导体碳化物层的非六边形表面上的半导体原子对碳原子有选择性的蒸发。 随着半导体原子被选择性地去除，半导体 - 碳合金层表面上的碳浓度增加。 尽管半导体 - 碳合金层的表面具有非六边形对称性，但剩余的碳原子可以聚结形成具有六边形对称性的石墨烯层。

    Charging-free electron beam cure of dielectric material
    2.
    发明授权
    Charging-free electron beam cure of dielectric material 失效
    无电荷电子束固化电介质材料

    公开(公告)号：US08525123B2

    公开(公告)日：2013-09-03

    申请号：US12013799

    申请日：2008-01-14

    申请人： Christos D. Dimitrakopoulos ,  Kam L. Lee ,  Robert L. Wisnieff

    发明人： Christos D. Dimitrakopoulos ,  Kam L. Lee ,  Robert L. Wisnieff

    IPC分类号： H01J37/304

    CPC分类号： H01L21/76825 ,  B29C71/04 ,  B29C2035/0877 ,  H01J37/026 ,  H01J37/317 ,  H01J2237/0044 ,  H01J2237/024 ,  H01J2237/047 ,  H01J2237/3156 ,  H01L21/3105 ,  H01L21/76835

    摘要： An ultra low-k dielectric material layer is formed on a semiconductor substrate. In one embodiment, a grid of wires is placed at a distance above a top surface of the ultra low-k dielectric material layer and is electrically biased such that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. In another embodiment, a polymeric conductive layer is formed directly on the ultra low-k dielectric material layer and is electrically biased so that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. By maintaining the total electron emission coefficient at 1.0, charging of the substrate is avoided, thus protecting any device on the substrate from any adverse changes in electrical characteristics.

    摘要翻译： 在半导体基板上形成超低k电介质材料层。 在一个实施例中，电线格栅放置在超低k电介质材料层的顶表面上方的距离处，并被电偏置，使得在电子束固化中使用的电子的能量下，总电子发射系数为1.0 超低k电介质材料层。 在另一个实施例中，聚合物导电层直接形成在超低k电介质材料层上并被电偏置，使得在超低k电介质的电子束固化中使用的电子能量下，总电子发射系数变为1.0 材料层。 通过将总电子发射系数保持在1.0，避免了衬底的充电，从而保护衬底上的任何器件免受电特性的任何不利变化。

    SILICON PHOTONIC CHIP OPTICAL COUPLING STRUCTURES
    3.
    发明申请
    SILICON PHOTONIC CHIP OPTICAL COUPLING STRUCTURES 有权
    硅光电芯片光耦合结构

    公开(公告)号：US20130182998A1

    公开(公告)日：2013-07-18

    申请号：US13353118

    申请日：2012-01-18

    申请人： Paul S. Andry ,  Russell A. Budd ,  Frank R. Libsch ,  Robert L. Wisnieff

    发明人： Paul S. Andry ,  Russell A. Budd ,  Frank R. Libsch ,  Robert L. Wisnieff

    IPC分类号： G02B6/42 ,  G02B6/32

    CPC分类号： G02B6/4204 ,  G02B6/34

    摘要： A silicon photonic chip is provided. An active silicon layer that includes a photonic device is on a front side of the silicon photonic chip. A silicon substrate that includes an etched backside cavity is on a backside of the silicon photonic chip. A microlens is integrated into the etched backside cavity. A buried oxide layer is located between the active silicon layer and the silicon substrate. The buried oxide layer is an etch stop for the etched backside cavity.

    摘要翻译： 提供硅光子芯片。 包括光子器件的有源硅层位于硅光子芯片的前侧。 包括蚀刻的背面腔的硅衬底位于硅光子芯片的背面。 将微透镜集成到蚀刻的背面腔中。 掩埋氧化物层位于有源硅层和硅衬底之间。 掩埋氧化物层是用于蚀刻的背面腔的蚀刻停止。

    Graphene nanoribbons, method of fabrication and their use in electronic devices
    4.
    发明授权
    Graphene nanoribbons, method of fabrication and their use in electronic devices 有权
    石墨烯纳米带，其制造方法及其在电子设备中的应用

    公开(公告)号：US08361853B2

    公开(公告)日：2013-01-29

    申请号：US12902620

    申请日：2010-10-12

    申请人： Guy Cohen ,  Christos D. Dimitrakopoulos ,  Alfred Grill ,  Robert L. Wisnieff

    发明人： Guy Cohen ,  Christos D. Dimitrakopoulos ,  Alfred Grill ,  Robert L. Wisnieff

    IPC分类号： H01L29/06 ,  H01L21/336

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/1606 ,  H01L29/66439 ,  H01L29/78684

    摘要： The present disclosure provides a semiconductor structure including a nanoribbon-containing layer of alternating graphene nanoribbons separated by alternating insulating ribbons. The alternating graphene nanoribbons are parallel to a surface of an underlying substrate and, in some embodiments, might be oriented along crystallographic directions of the substrate. The alternating insulating ribbons may comprise hydrogenated graphene, i.e., graphane, fluorinated graphene, or fluorographene. The semiconductor structure mentioned above can be formed by selectively converting portions of an initial graphene layer into alternating insulating ribbons, while the non-converted portions of the initial graphene form the alternating graphene nanoribbons. Semiconductor devices such as, for example, field effect transistors, can be formed atop the semiconductor structure provided in the present disclosure.

    摘要翻译： 本公开提供了一种半导体结构，其包括由交替的绝缘带分开的交替的石墨烯纳米带的纳米带层。 交替的石墨烯纳米带平行于下面的基底的表面，并且在一些实施方案中可以沿着基底的结晶方向取向。 交替的绝缘带可以包括氢化石墨烯，即塔帕尼，氟化石墨烯或荧光荧光物质。 上述半导体结构可以通过将初始石墨烯层的部分选择性地转换为交替绝缘带而形成，而初始石墨烯的未转化部分形成交替的石墨烯纳米带。 诸如场效应晶体管的半导体器件可以形成在本公开中提供的半导体结构的顶部。

    MOSFET STRUCTURE WITH ULTRA-LOW K SPACER
    8.
    发明申请
    MOSFET STRUCTURE WITH ULTRA-LOW K SPACER 审中-公开
    MOSFET结构与超低K间隔

    公开(公告)号：US20080128766A1

    公开(公告)日：2008-06-05

    申请号：US12030921

    申请日：2008-02-14

    申请人： Elbert E. Huang ,  Philip J. Oldiges ,  Ghavam G. Shahidi ,  Christy S. Tyberg ,  Xinlin Wang ,  Robert L. Wisnieff

    发明人： Elbert E. Huang ,  Philip J. Oldiges ,  Ghavam G. Shahidi ,  Christy S. Tyberg ,  Xinlin Wang ,  Robert L. Wisnieff

    IPC分类号： H01L29/94 ,  H01L21/336

    CPC分类号： H01L29/4991 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. The multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. Alternatively, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. The multi-layer spacer may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.

    摘要翻译： MOSFET结构和制造该结构的方法包括多层侧壁间隔物，以抑制栅极导体和源极/漏极延伸之间的寄生重叠电容，而不降低驱动电流，从而影响整体MOSFET性能。 多层侧壁间隔物形成有介电常数等于1的间隙层和可渗透的低K（例如，小于3.5）的电介质层。 或者，多层侧壁间隔物形成有介电常数值小于约三的第一L形介电层和第二电介质层。 多层间隔物也可以具有第三氮化物或氧化物隔离层。 该第三间隔层提供增加的结构完整性。

    Thin film transistor and multilayer film structure and manufacturing method of same
    9.
    发明授权
    Thin film transistor and multilayer film structure and manufacturing method of same 失效
    薄膜晶体管和多层膜结构及其制造方法相同

    公开(公告)号：US07037769B2

    公开(公告)日：2006-05-02

    申请号：US10890759

    申请日：2004-07-14

    申请人： Peter M. Fryer ,  Robert L. Wisnieff ,  Takatoshi Tsujimura

    发明人： Peter M. Fryer ,  Robert L. Wisnieff ,  Takatoshi Tsujimura

    IPC分类号： H01L21/00 ,  G02F1/136

    CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L27/1292 ,  H01L29/41733 ,  H01L29/66757 ,  H01L29/78609 ,  H01L29/78633 ,  H01L29/78666

    摘要： The present invention is directed to a thin film transistor (and related multilayer structures) that includes: source and drain electrodes 14 and 15 disposed at a specified interval above an insulating substrate 11 and formed by printing-and-plating; an a-Si film 16 disposed for the source and drain electrodes 14 and 15; a gate insulating film 17 laminated on the a-Si film 16; and a gate electrode 18 laminated on the gate insulating film 17 and formed by printing-and-plating. The a-Si film 16 and the gate insulating film 17 have an offset region 20 that uniformly extends beyond the dimensions of the gate electrode 18.

    摘要翻译： 本发明涉及一种薄膜晶体管（及相关的多层结构），其包括：以绝缘基板11上方的特定间隔设置并通过印刷和电镀形成的源极和漏极14和15; 为源极和漏极14和15设置的a-Si膜16; 层叠在a-Si膜16上的栅极绝缘膜17; 以及层叠在栅极绝缘膜17上并通过印刷和电镀形成的栅电极18。 a-Si膜16和栅极绝缘膜17具有均匀地延伸超过栅电极18的尺寸的偏移区域20。

    Method for testing a partially constructed electronic circuit
    10.
    发明授权
    Method for testing a partially constructed electronic circuit 失效
    用于测试部分构造的电子电路的方法

    公开(公告)号：US5561381A

    公开(公告)日：1996-10-01

    申请号：US2293

    申请日：1993-01-08

    申请人： Leslie C. Jenkins ,  Robert L. Wisnieff

    发明人： Leslie C. Jenkins ,  Robert L. Wisnieff

    IPC分类号： G01R27/26 ,  G01R31/26 ,  G02F1/13 ,  G02F1/136 ,  G02F1/1368 ,  G09G3/36 ,  H01L21/66

    CPC分类号： G01R31/2621 ,  G01R27/2605

    摘要： A sense circuit for detecting charge on a TFT/LCD cell capacitor, which comprises a first, integrating circuit attached to the TFT/LCD cell capacitor through a data line, wherein the data line is connected to the cell capacitance through a thin film transistor is disclosed. The thin film transistor including a gate, a drain and a source, wherein the source is connected to the cell capacitor and the drain is connected to the data line. A first, gate supply voltage adapted to drive the gate of the thin film transistor. And a reset circuit adapted to reset the integrating circuit. This embodiment may further include a source for charging said cell capacitor prior to measuring the charge. Further, a method of testing a partially constructed electronic circuit, for example the cell of an LCD, prior to installation of the backplate is also disclosed. The partial circuit comprising an array of contact electrodes, for example cell pad electrodes and an array of address electrodes, for example gate electrodes. The address electrodes being electrically connected to the contact electrodes. The method comprising the steps of providing the partial circuit with a test electrode, for example an adjacent data electrode extending alongside but spaced from at least a first contact electrode; and measuring the capacitance between the first contact electrode and the test electrode.

    摘要翻译： 一种用于检测TFT / LCD单元电容器上的电荷的感测电路，其包括通过数据线连接到TFT / LCD单元电容器的第一集成电路，其中数据线通过薄膜晶体管连接到单元电容， 披露 薄膜晶体管包括栅极，漏极和源极，其中源极连接到电池电容器，漏极连接到数据线。 第一栅极电源电压，适于驱动薄膜晶体管的栅极。 以及复位电路，其适于复位积分电路。 该实施例还可以包括用于在测量电荷之前对所述电池电容器充电的源。 此外，还公开了在安装背板之前测试部分构造的电子电路（例如LCD的单元）的方法。 该部分电路包括接触电极的阵列，例如电池垫电极和寻址电极阵列，例如栅电极。 地址电极电连接到接触电极。 该方法包括以下步骤：向部分电路提供测试电极，例如沿至少一个第一接触电极间隔开的相邻数据电极; 并测量第一接触电极和测试电极之间的电容。