公开(公告)号：US09337093B2

公开(公告)日：2016-05-10

申请号：US13182944

申请日：2011-07-14

申请人： Daisuke Oshida ,  Ippei Kume ,  Makoto Ueki ,  Manabu Iguchi ,  Naoya Inoue ,  Takuya Maruyama ,  Toshiji Taiji ,  Hirokazu Katsuyama

发明人： Daisuke Oshida ,  Ippei Kume ,  Makoto Ueki ,  Manabu Iguchi ,  Naoya Inoue ,  Takuya Maruyama ,  Toshiji Taiji ,  Hirokazu Katsuyama

IPC分类号： H01L21/283 ,  H01L21/768 ,  H01L21/3105 ,  H01L23/532 ,  H01L21/02

CPC分类号： H01L21/76883 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/3105 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device includes an insulating film that is formed using a cyclic siloxane having a six-membered ring structure as a raw material; a trench that is formed in the insulating film; and a interconnect that is configured by a metal film embedded in the trench. In the semiconductor device, a modified layer is formed on a bottom surface of the trench, in which the number of carbon atoms and/or the number of nitrogen atoms per unit volume is larger than that inside the insulating film.

摘要翻译： 半导体器件包括使用具有六元环结构的环状硅氧烷作为原料形成的绝缘膜; 在绝缘膜中形成的沟槽; 以及由嵌入在沟槽中的金属膜构成的互连。 在半导体装置中，在沟槽的底面上形成改性层，其中每单位体积的碳原子数和/或氮原子数大于绝缘膜内部。

公开(公告)号：US09085215B2

公开(公告)日：2015-07-21

申请号：US14118349

申请日：2011-05-18

申请人： Hirohito Kawai ,  Naoya Inoue ,  Seiichi Tsunoda ,  Takaaki Goto ,  Yoichiro Higuchi

发明人： Hirohito Kawai ,  Naoya Inoue ,  Seiichi Tsunoda ,  Takaaki Goto ,  Yoichiro Higuchi

IPC分类号： B60H1/00 ,  B60L1/00 ,  B60L11/14 ,  B60L11/18 ,  G08C17/02

CPC分类号： B60H1/00642 ,  B60H1/00657 ,  B60H1/00771 ,  B60H1/00807 ,  B60L1/003 ,  B60L11/14 ,  B60L11/1816 ,  B60L2240/34 ,  B60L2240/622 ,  B60L2240/662 ,  B60L2240/70 ,  B60L2240/80 ,  B60L2250/16 ,  B60L2260/56 ,  G08C17/02 ,  G08C2201/93 ,  Y02T10/70 ,  Y02T10/7005 ,  Y02T10/7072 ,  Y02T10/7077 ,  Y02T10/7291 ,  Y02T90/14 ,  Y02T90/16 ,  Y02T90/162

摘要： An estimated temperature range is calculated by adding a plus-side temperature width to the temperature detected by a temperature sensor within the cabin of a vehicle and subtracting a minus-side temperature width therefrom, and is displayed on the display of a mobile terminal as a temperature state of the cabin. When cooling is performed, the plus-side temperature width is made greater than the minus-side temperature width. Also, the plus-side temperature width is narrowed with elapse of time from the start of pre-air-conditioning. With this operation, the temperature state of the vehicle cabin from the start of the pre-air-conditioning can be properly communicated to a vehicle user.

摘要翻译： 通过对由车辆内的温度传感器检测到的温度加上正面温度宽度并从其中减去负侧温度宽度来计算估计的温度范围，并将其显示在移动终端的显示器上 舱室温度状态。 当进行冷却时，使正面温度宽度大于负侧温度宽度。 此外，正面温度宽度随着从预先空调开始经过的时间变窄。 通过该操作，可以将车厢从预先空调开始的温度状态适当地传递给车辆用户。

公开(公告)号：US08648441B2

公开(公告)日：2014-02-11

申请号：US13106590

申请日：2011-05-12

申请人： Kenichiro Hijioka ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

发明人： Kenichiro Hijioka ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

IPC分类号： H01L21/02

CPC分类号： H01L27/10894 ,  H01L21/76811 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.

摘要翻译： 半导体器件具有基板; 形成在所述基板上的多层互连，并且具有多个互连层，每个互连层由布置在其中的互连和绝缘层构成; 在平面图形成在基板上的存储器电路区域中的存储电路，并且具有外围电路和嵌入多层互连中的至少一个电容元件; 以及形成在所述基板上的逻辑电路区域中的逻辑电路，其中所述电容器元件由下电极，电容器绝缘膜，上电极，嵌入电极和上互连构成; 上互连的顶表面和构成与上互连的同一互连层中形成的逻辑电路的互连的顶表面与同一平面对准。

公开(公告)号：US08629529B2

公开(公告)日：2014-01-14

申请号：US12519706

申请日：2007-12-25

申请人： Naoya Inoue ,  Ippei Kume ,  Jun Kawahara ,  Yoshihiro Hayashi

发明人： Naoya Inoue ,  Ippei Kume ,  Jun Kawahara ,  Yoshihiro Hayashi

IPC分类号： H01L27/06

CPC分类号： H01L23/5228 ,  H01L23/5223 ,  H01L23/53238 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device is produced by fabricating a capacitor element including a lower electrode, a capacitor insulating film, and an upper electrode, and a thin-film resistor element, in the same step. As the lower electrode of the capacitor element is lined with a lower layer wiring layer (Cu wiring), the lower electrode has extremely low resistance substantially. As such, even if the film thickness of the lower electrode becomes thinner, parasitic resistance does not increased. The resistor element is formed to have the same film thickness as that of the lower electrode of the capacitor element. Since the film thickness of the lower electrode is thin, it works as a resistor having high resistance. In the top layer of the passive element, a passive element cap insulating film is provided, which works as an etching stop layer when etching a contact of the upper electrode of the capacitor element.

摘要翻译： 通过在同一步骤中制造包括下电极，电容器绝缘膜和上电极的电容器元件和薄膜电阻器元件来制造半导体器件。 由于电容器元件的下电极衬有下层布线层（Cu布线），所以下电极具有极低的电阻。 因此，即使下电极的膜厚变薄，寄生电阻也不会增加。 电阻元件形成为具有与电容器元件的下电极相同的膜厚度。 由于下部电极的膜厚薄，所以作为具有高电阻的电阻器。 在无源元件的顶层中，设置无源元件帽绝缘膜，当蚀刻电容器元件的上电极的接触时，其被用作蚀刻停止层。

公开(公告)号：US08618537B2

公开(公告)日：2013-12-31

申请号：US13067386

申请日：2011-05-27

申请人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L29/10

CPC分类号： H01L29/7869 ,  H01L27/0688 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/45 ,  H01L29/458

摘要： A semiconductor device includes, in a first region over a semiconductor substrate, a first insulating layer, a first wiring, a second insulating layer, a third insulating layer, and a via and a second wiring embedded in the second insulating layer and the third insulating layer through a barrier metal, and includes, in a second region, the first insulating layer, a gate electrode, the second insulating layer, a semiconductor layer located, the third insulating layer, and a first electric conductor and a second electric conductor embedded in the third insulating layer so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view through a barrier metal and coupled to the semiconductor layer through the barrier metal.

摘要翻译： 半导体器件包括在半导体衬底上的第一区域中，第一绝缘层，第一布线，第二绝缘层，第三绝缘层以及嵌入第二绝缘层中的通孔和第二布线，以及第三绝缘层 并且在第二区域中包括第一绝缘层，栅电极，第二绝缘层，位于第三绝缘层和第一导电体中的半导体层，以及嵌入在第二绝缘层中的第二导电体 第三绝缘层，以通过势垒金属在平面图中将栅电极夹在与半导体层重叠的位置，并通过阻挡金属耦合到半导体层。

公开(公告)号：US20130082765A1

公开(公告)日：2013-04-04

申请号：US13610241

申请日：2012-09-11

申请人： Kishou KANEKO ,  Naoya INOUE ,  Yoshihiro HAYASHI

发明人： Kishou KANEKO ,  Naoya INOUE ,  Yoshihiro HAYASHI

IPC分类号： G05F3/08

CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/00011 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2924/00012

摘要： A semiconductor device includes a logic circuit and an active element circuit. The logic circuit is provided with semiconductor elements formed in a semiconductor substrate. The active element circuit is provided with transistors formed using semiconductor layers formed over a diffusion insulating film formed above a semiconductor substrate. The active element circuit is controlled by the logic circuit.

摘要翻译： 半导体器件包括逻辑电路和有源元件电路。 逻辑电路设置有形成在半导体衬底中的半导体元件。 有源元件电路设置有使用在半导体衬底上形成的扩散绝缘膜上形成的半导体层形成的晶体管。 有源元件电路由逻辑电路控制。

公开(公告)号：US20130056850A1

公开(公告)日：2013-03-07

申请号：US13593084

申请日：2012-08-23

申请人： Ippei KUME ,  Kenichiro Hijioka ,  Naoya Inoue ,  Hiroyuki Kunishima ,  Manabu Iguchi ,  Hiroki Shirai

发明人： Ippei KUME ,  Kenichiro Hijioka ,  Naoya Inoue ,  Hiroyuki Kunishima ,  Manabu Iguchi ,  Hiroki Shirai

IPC分类号： H01L27/04 ,  H01L21/02

CPC分类号： H01L27/10894 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/90

摘要： To provide a semiconductor device featuring reduced variation in capacitor characteristics. In the semiconductor device, a protective layer is provided at the periphery of the upper end portion of a recess (hole). This protective layer has a dielectric constant higher than that of an insulating layer placed in the same layer as the protective layer and configuring a multilayer wiring layer placed in a logic circuit region.

摘要翻译： 提供具有降低的电容特性变化的半导体器件。 在半导体装置中，在凹部（孔）的上端部的周围设有保护层。 该保护层的介电常数高于与保护层位于同一层的绝缘层的介电常数，并且构成放置在逻辑电路区域中的多层布线层。

公开(公告)号：US08275510B2

公开(公告)日：2012-09-25

申请号：US12670470

申请日：2008-07-25

申请人： Naoto Tanaka ,  Shinya Toyoda ,  Naoya Inoue ,  Tadashi Tamura ,  Akira Hino ,  Yasunari Matsui

发明人： Naoto Tanaka ,  Shinya Toyoda ,  Naoya Inoue ,  Tadashi Tamura ,  Akira Hino ,  Yasunari Matsui

IPC分类号： G06F19/00

CPC分类号： F16H61/12 ,  F16H59/70 ,  F16H61/66259 ,  F16H61/66272 ,  F16H2061/1208 ,  F16H2061/1264 ,  Y10T477/387 ,  Y10T477/624 ,  Y10T477/62427

摘要： An ECU executes a program including the steps of determining that a change speed solenoid is abnormal when a target speed ratio falls within a predetermined range, an upshift is recognized and the change speed solenoid is abnormal; determining that the change speed solenoid is normal when the change speed solenoid is not abnormal; determining that a belt pinch pressure solenoid is abnormal when the target speed ratio is substantially equal to a speed ratio γmin on a maximum speed-increase side and the target speed ratio is not substantially equal to an actual speed ratio; and determining that the belt pinch pressure solenoid is normal when the target speed ratio is substantially equal to the actual speed ratio.

摘要翻译： ECU执行程序，包括当目标速度比落在预定范围内时确定变速螺线管异常的步骤，识别升档并且变速螺线管异常; 当变速电磁铁不是异常时，确定变速电磁铁正常; 当目标速度比基本上等于最大增速侧的速比γmin并且目标速比基本上不等于实际速比时，确定皮带夹紧压力螺线管是异常的; 并且当目标速度比基本上等于实际速比时，确定皮带夹紧压力螺线管是正常的。

公开(公告)号：US20120228728A1

公开(公告)日：2012-09-13

申请号：US13399475

申请日：2012-02-17

申请人： Makoto UEKI ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Makoto UEKI ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L29/82 ,  H01L21/8246

CPC分类号： H01L43/12 ,  H01L27/228 ,  H01L43/08

摘要： A semiconductor device in which MRAM is formed in a wiring layer A contained in a multilayered wiring layer, the MRAM having at least two first magnetization pinning layers in contact with a first wiring formed in a wiring layer and insulated from each other, a free magnetization layer overlapping the two first magnetization pinning layers in a plan view, and connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layer situated over the non-magnetic layer.

摘要翻译： 一种半导体器件，其中在包含在多层布线层中的布线层A中形成MRAM，所述MRAM具有与形成在布线层中并彼此绝缘的第一布线接触的至少两个第一磁化闭塞层，自由磁化 层在平面图中与两个第一磁化钉扎层重叠，并与第一磁化钉扎层，位于自由磁化层上方的非磁性层和位于非磁性层上的第二磁化钉扎层连接。

公开(公告)号：US20120115253A1

公开(公告)日：2012-05-10

申请号：US13373098

申请日：2011-11-04

申请人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L43/12

CPC分类号： H01L23/552 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor apparatus includes forming a semiconductor device on a principal surface of a substrate, in which the semiconductor device includes an interconnect layer, forming a buffer film which covers the semiconductor device and prevents diffusion of a magnetic material, and forming a magnetic shielding film which covers the buffer film and includes the magnetic material.

摘要翻译： 一种半导体装置的制造方法，其特征在于，在基板的主面上形成半导体装置，所述半导体装置具有互连层，形成覆盖所述半导体装置的缓冲膜，防止磁性材料的扩散，形成 覆盖缓冲膜并包括磁性材料的磁屏蔽膜。