公开(公告)号：US08558334B2

公开(公告)日：2013-10-15

申请号：US13399475

申请日：2012-02-17

Applicant: Makoto Ueki ,  Naoya Inoue ,  Yoshihiro Hayashi

Inventor： Makoto Ueki ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC: H01L29/82 ,  H01L23/552 ,  H01L27/08 ,  H01L21/00

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/08

Abstract: A semiconductor device in which MRAM is formed in a wiring layer A contained in a multilayered wiring layer, the MRAM having at least two first magnetization pinning layers in contact with a first wiring formed in a wiring layer and insulated from each other, a free magnetization layer overlapping the two first magnetization pinning layers in a plan view, and connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layer situated over the non-magnetic layer.

Abstract translation: 一种半导体器件，其中MRAM形成在包含在多层布线层中的布线层A中，所述MRAM具有与形成在布线层中并彼此绝缘的第一布线接触的至少两个第一磁化闭塞层，自由磁化 层在平面图中与两个第一磁化钉扎层重叠，并与第一磁化钉扎层，位于自由磁化层上方的非磁性层和位于非磁性层上的第二磁化钉扎层连接。

公开(公告)号：US20120228728A1

公开(公告)日：2012-09-13

申请号：US13399475

申请日：2012-02-17

Applicant: Makoto UEKI ,  Naoya Inoue ,  Yoshihiro Hayashi

Inventor： Makoto UEKI ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC: H01L29/82 ,  H01L21/8246

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/08

Abstract: A semiconductor device in which MRAM is formed in a wiring layer A contained in a multilayered wiring layer, the MRAM having at least two first magnetization pinning layers in contact with a first wiring formed in a wiring layer and insulated from each other, a free magnetization layer overlapping the two first magnetization pinning layers in a plan view, and connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layer situated over the non-magnetic layer.

Abstract translation: 一种半导体器件，其中在包含在多层布线层中的布线层A中形成MRAM，所述MRAM具有与形成在布线层中并彼此绝缘的第一布线接触的至少两个第一磁化闭塞层，自由磁化 层在平面图中与两个第一磁化钉扎层重叠，并与第一磁化钉扎层，位于自由磁化层上方的非磁性层和位于非磁性层上的第二磁化钉扎层连接。

公开(公告)号：US09337093B2

公开(公告)日：2016-05-10

申请号：US13182944

申请日：2011-07-14

Applicant: Daisuke Oshida ,  Ippei Kume ,  Makoto Ueki ,  Manabu Iguchi ,  Naoya Inoue ,  Takuya Maruyama ,  Toshiji Taiji ,  Hirokazu Katsuyama

Inventor： Daisuke Oshida ,  Ippei Kume ,  Makoto Ueki ,  Manabu Iguchi ,  Naoya Inoue ,  Takuya Maruyama ,  Toshiji Taiji ,  Hirokazu Katsuyama

IPC: H01L21/283 ,  H01L21/768 ,  H01L21/3105 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L21/76883 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/3105 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device includes an insulating film that is formed using a cyclic siloxane having a six-membered ring structure as a raw material; a trench that is formed in the insulating film; and a interconnect that is configured by a metal film embedded in the trench. In the semiconductor device, a modified layer is formed on a bottom surface of the trench, in which the number of carbon atoms and/or the number of nitrogen atoms per unit volume is larger than that inside the insulating film.

Abstract translation: 半导体器件包括使用具有六元环结构的环状硅氧烷作为原料形成的绝缘膜; 在绝缘膜中形成的沟槽; 以及由嵌入在沟槽中的金属膜构成的互连。 在半导体装置中，在沟槽的底面上形成改性层，其中每单位体积的碳原子数和/或氮原子数大于绝缘膜内部。

公开(公告)号：US08378341B2

公开(公告)日：2013-02-19

申请号：US12654205

申请日：2009-12-14

Applicant: Yoshihiro Hayashi ,  Naoya Inoue ,  Kishou Kaneko

Inventor： Yoshihiro Hayashi ,  Naoya Inoue ,  Kishou Kaneko

IPC: H01L29/18 ,  H01L21/00

CPC classification number: H01L21/76807 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/242 ,  H01L29/41 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/792

Abstract: A semiconductor device of the present invention has a first interconnect layer formed over the semiconductor substrate, and a semiconductor element; the first interconnect layer has an insulating layer, and a first interconnect filled in a surficial portion of the insulating layer; the semiconductor element has a semiconductor layer, a gate insulating film, and a gate electrode; the semiconductor layer is positioned over the first interconnect layer; the gate insulating film is positioned over or below semiconductor layer; and the gate electrode is positioned on the opposite side of the semiconductor layer while placing the gate insulating film in between.

Abstract translation: 本发明的半导体器件具有形成在半导体衬底上的第一互连层和半导体元件; 所述第一互连层具有绝缘层，以及填充在所述绝缘层的表面部分中的第一互连层; 半导体元件具有半导体层，栅极绝缘膜和栅电极; 半导体层位于第一互连层上方; 栅绝缘膜位于半导体层之上或之下; 并且栅极电极位于半导体层的相反侧，同时将栅极绝缘膜放置在其间。

公开(公告)号：US06300212B1

公开(公告)日：2001-10-09

申请号：US09124067

申请日：1998-07-29

Applicant: Naoya Inoue ,  Yoshihiro Hayashi

Inventor： Naoya Inoue ,  Yoshihiro Hayashi

IPC: H01L2120

CPC classification number: C23C14/088 ,  H01L21/31691 ,  H01L28/55

Abstract: In a method and an apparatus for manufacturing a semiconductor device which has a capacitor consisting of a layered structure of a lower electrode, a ferroelectric layer made of a composite metal oxide such as PZT and an upper electrode in a predetermined region on a semiconductor substrate, the lower electrode, the ferroelectric layer and the upper electrode are successively formed in an atmosphere isolated from the air. For the duration after forming the ferroelectric layer till starting the formation of the upper electrode, it is desirable to introduce a gas such as an inert gas or an inert gas with oxygen into the atmosphere in the vicinity of the substrate to keep the atmosphere within a predetermined pressure range.

Abstract translation: 在半导体装置的制造方法和装置中，具有由下电极构成的电容器，由复合金属氧化物如PZT制成的铁电层和半导体基板上的预定区域中的上电极， 下部电极，铁电层和上部电极依次形成在与空气隔离的气氛中。 在形成铁电层直到开始形成上电极的持续时间之后，期望将惰性气体或惰性气体的气体与氧气引入到基板附近的气氛中，以将气氛保持在 预定压力范围。

公开(公告)号：US08890289B2

公开(公告)日：2014-11-18

申请号：US13358133

申请日：2012-01-25

Applicant: Kenzo Manabe ,  Naoya Inoue ,  Kenichiro Hijioka ,  Yoshihiro Hayashi

Inventor： Kenzo Manabe ,  Naoya Inoue ,  Kenichiro Hijioka ,  Yoshihiro Hayashi

IPC: H01L29/02 ,  H01L21/02 ,  H01L27/108 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L27/1085 ,  H01L21/768 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.

Abstract translation: 一种半导体器件，包括：多层布线层，位于基板的上方，其中堆叠由布线和绝缘层构成的多个布线层; 存储电路，其形成在所述基板的存储电路区域中，并且具有嵌入在位于所述多层布线层中的凹部的电容元件; 形成在基板的逻辑电路区域中的逻辑电路; 层叠在由下部电极，电容绝缘膜和上部电极构成的电容元件上的上部耦合布线; 以及形成在构成逻辑电路的布线的上表面上的盖层。 上部连接线的上表面和盖膜的上表面设置在同一平面上。

公开(公告)号：US08373256B2

公开(公告)日：2013-02-12

申请号：US12770050

申请日：2010-04-29

Applicant: Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

Inventor： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L23/5225 ,  H01L23/5227 ,  H01L27/228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a semiconductor substrate; a semiconductor element formed on a principal surface of the semiconductor substrate and having a multiple-layered interconnect layer; and a heterostructure magnetic shield covering the semiconductor element. The heterostructure magnetic shield includes a first magnetic shield layered structure and a second magnetic shield layered structure that covers the first magnetic shield layered structure. Each of a first and a second magnetic shield layered structures includes a magnetic shielding film composed of a magnetic substance and covering the semiconductor element and a buffer film disposed between the semiconductor element and the magnetic shield films and preventing a diffusion of the magnetic substance.

Abstract translation: 半导体器件包括：半导体衬底; 半导体元件，其形成在所述半导体衬底的主表面上并具有多层互连层; 和覆盖半导体元件的异质结构磁屏蔽。 异质结构磁屏蔽包括第一磁屏蔽分层结构和覆盖第一磁屏蔽分层结构的第二磁屏蔽分层结构。 第一和第二磁屏蔽分层结构中的每一个包括由磁性物质构成并覆盖半导体元件的磁屏蔽膜和设置在半导体元件和磁屏蔽膜之间的缓冲膜，并且防止磁性物质的扩散。

公开(公告)号：US20100207093A1

公开(公告)日：2010-08-19

申请号：US12656728

申请日：2010-02-16

Applicant: Naoya Inoue ,  Yoshihiro Hayashi ,  Kishou Kaneko

Inventor： Naoya Inoue ,  Yoshihiro Hayashi ,  Kishou Kaneko

IPC: H01L45/00 ,  H01L21/441

CPC classification number: H01L21/76807 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

Abstract: Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

Abstract translation: 提供了一种半导体器件，其包括基板，以及形成在基板上的第一布线层，第二布线层和开关通孔。 第一布线层具有形成在其中的第一布线，并且第二布线层具有形成在其中的第二布线。 开关通孔连接第一布线和第二布线。 开关通孔至少在其底部包括包括电阻变化层的开关元件。 电阻变化层的电阻值根据施加到其上的电场的历史而变化。

公开(公告)号：US20070291441A1

公开(公告)日：2007-12-20

申请号：US11571084

申请日：2005-06-23

Applicant: Naoya Inoue ,  Yoshihiro Hayashi

Inventor： Naoya Inoue ,  Yoshihiro Hayashi

IPC: H01G4/35

CPC classification number: H01L23/5223 ,  H01L27/0629 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: In a capacitor element in which a highly dielectric metal oxide film formed between wiring layers is used as a capacitor insulation film, the diffusion and thermal oxidation of a lower-layer wiring material are reduced, and the surface on which a thin capacitor insulation film that constitutes a capacitor element is formed is kept flat. A lower electrode (111b) having the ability to prevent diffusion of the wiring material is embedded and formed so as to be in direct contact with a lower-layer wiring (105) in a prescribed area of a wiring cap film (103), and the surface on which the capacitor insulation film is formed is flat. The wiring cap film functions to prevent diffusion and oxidation of the wiring material formed on a wiring disposed in a lower layer of the capacitor element.

Abstract translation: 在使用在布线层之间形成的高介电金属氧化物膜作为电容绝缘膜的电容器元件中，下层布线材料的扩散和热氧化被降低，并且薄电容绝缘膜的表面 构成电容器元件形成时保持平坦。 具有防止布线材料扩散的能力的下电极（111b）嵌入并形成为与配线帽膜（103）的规定区域中的下层布线（105）直接接触， 并且其上形成有电容器绝缘膜的表面是平坦的。 布线帽膜用于防止形成在布置在电容器元件的下层中的布线上的布线材料的扩散和氧化。

公开(公告)号：US08648441B2

公开(公告)日：2014-02-11

申请号：US13106590

申请日：2011-05-12

Applicant: Kenichiro Hijioka ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

Inventor： Kenichiro Hijioka ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

IPC: H01L21/02

CPC classification number: H01L27/10894 ,  H01L21/76811 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.

Abstract translation: 半导体器件具有基板; 形成在所述基板上的多层互连，并且具有多个互连层，每个互连层由布置在其中的互连和绝缘层构成; 在平面图形成在基板上的存储器电路区域中的存储电路，并且具有外围电路和嵌入多层互连中的至少一个电容元件; 以及形成在所述基板上的逻辑电路区域中的逻辑电路，其中所述电容器元件由下电极，电容器绝缘膜，上电极，嵌入电极和上互连构成; 上互连的顶表面和构成与上互连的同一互连层中形成的逻辑电路的互连的顶表面与同一平面对准。