公开(公告)号：US20100323489A1

公开(公告)日：2010-12-23

申请号：US12805825

申请日：2010-08-20

申请人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

发明人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

IPC分类号： H01L21/02

CPC分类号： H01L45/143 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02672 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/66136 ,  H01L29/66204 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.

公开(公告)号：US07563677B2

公开(公告)日：2009-07-21

申请号：US11531239

申请日：2006-09-12

申请人： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung Kim ,  Jung-Hwan Oh ,  Young-Sub You

发明人： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung Kim ,  Jung-Hwan Oh ,  Young-Sub You

IPC分类号： H01L21/336

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621

摘要： A recessed gate electrode structure includes a first recess and a second recess in communication with the first recess both formed in a substrate. The second recess is larger than the first recess. A gate dielectric layer is formed on a top surface of the substrate and on an inner surface of the first and second recesses. A first polysilicon layer fills the first recess and is doped with impurities at a first impurity density. A second polysilicon layer fills the second recess and is doped with the impurities at a second impurity density. A void is defined within the second polysilicon layer. A third polysilicon layer is formed on the gate dielectric and first polysilicon layers and is doped with the impurities at a third impurity density. Due to impurities in the second polysilicon layer, migration of the void within the second recess may be substantially prevented.

摘要翻译： 凹陷栅极电极结构包括第一凹部和与形成在基板中的第一凹部连通的第二凹部。 第二凹部比第一凹部大。 栅极电介质层形成在基板的顶表面上和第一凹槽和第二凹槽的内表面上。 第一多晶硅层填充第一凹槽并以第一杂质密度掺杂杂质。 第二多晶硅层填充第二凹槽，并以第二杂质密度掺杂杂质。 在第二多晶硅层内限定空隙。 在栅极电介质和第一多晶硅层上形成第三多晶硅层，并以第三杂质密度掺杂杂质。 由于第二多晶硅层中的杂质，可以基本上防止第二凹陷内的空隙的迁移。

公开(公告)号：US20080023770A1

公开(公告)日：2008-01-31

申请号：US11823765

申请日：2007-06-28

申请人： Kyoung-Seok Kim ,  Kong-Soo Lee ,  Sang-Jin Park ,  Sung-Kwan Kang ,  Ko-Eun Lee

发明人： Kyoung-Seok Kim ,  Kong-Soo Lee ,  Sang-Jin Park ,  Sung-Kwan Kang ,  Ko-Eun Lee

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L23/58

CPC分类号： H01L27/0688 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28556 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/8221 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108

摘要： The stacked semiconductor device includes a semiconductor substrate, a multi-layered insulation layer pattern having at least two insulation layer patterns and an opening, an active layer pattern formed on each of the insulation layer patterns, a first plug including single crystalline silicon-germanium, a second plug including single crystalline silicon, and a wiring electrically connected to the first plug and sufficiently filling up the opening. The insulation layer patterns are vertically stacked on the semiconductor substrate and the opening exposes an upper face of the semiconductor substrate. A side portion of the active layer pattern is exposed by the opening. The first plug is formed on the upper face of the semiconductor substrate to partially fill the opening. The second plug is partially formed on the first plug, and has substantially the same interface as that of the first plug.

摘要翻译： 叠层半导体器件包括半导体衬底，具有至少两个绝缘层图案和开口的多层绝缘层图案，形成在每个绝缘层图案上的有源层图案，包括单晶硅锗的第一插头， 包括单晶硅的第二插头和电连接到第一插头并充分填满开口的布线。 绝缘层图案垂直堆叠在半导体衬底上，并且开口暴露半导体衬底的上表面。 有源层图案的侧面部分由开口露出。 第一插头形成在半导体衬底的上表面上以部分地填充开口。 第二插头部分地形成在第一插头上，并且具有与第一插头基本相同的界面。

公开(公告)号：US06723662B2

公开(公告)日：2004-04-20

申请号：US10630101

申请日：2003-07-30

申请人： Kong-soo Lee ,  Jae-jong Han ,  Sung-eui Kim

发明人： Kong-soo Lee ,  Jae-jong Han ,  Sung-eui Kim

IPC分类号： H01L218242

CPC分类号： H01L21/28185 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/10894 ,  H01L27/11

摘要： Methods of forming gate oxide films in integrated circuit devices using wet or dry oxidization processes with a reduced amount of chloride are disclosed. A gate oxide film is formed on a substrate on an active region adjacent to a trench isolation region in a first gas atmosphere with a first amount of chloride. The gate oxide film is annealed in a second gas atmosphere including a second amount of chloride that is greater than the first amount.

摘要翻译： 公开了使用具有减少量的氯化物的湿式或干式氧化方法在集成电路器件中形成栅极氧化膜的方法。 在具有第一量氯化物的第一气体气氛中的与沟槽隔离区相邻的有源区上的衬底上形成栅极氧化膜。 栅极氧化膜在包括大于第一量的第二量氯化物的第二气体气氛中退火。

公开(公告)号：US07598141B2

公开(公告)日：2009-10-06

申请号：US11261266

申请日：2005-10-28

申请人： Chang-Hoon Lee ,  Sang-Jin Park ,  Won-Seok Yoo ,  Kong-Soo Lee

发明人： Chang-Hoon Lee ,  Sang-Jin Park ,  Won-Seok Yoo ,  Kong-Soo Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： A method of fabricating a static random access memory device includes selectively removing an insulating film and growing a single crystalline silicon layer using selective epitaxy growth, the single crystalline silicon layer being grown in a portion from which the insulating film is removed; recessing the insulating film; and depositing an amorphous silicon layer on the single crystalline silicon layer and the insulating film, such that the amorphous silicon layer partially surrounds a top surface and side surfaces of the single crystalline silicon layer.

摘要翻译： 一种制造静态随机存取存储器件的方法包括：使用选择性外延生长选择性地去除绝缘膜并生长单晶硅层，单晶硅层在除去绝缘膜的部分中生长; 使绝缘膜凹陷; 以及在所述单晶硅层和所述绝缘膜上沉积非晶硅层，使得所述非晶硅层部分地包围所述单晶硅层的顶表面和侧表面。

公开(公告)号：US20080286957A1

公开(公告)日：2008-11-20

申请号：US12122783

申请日：2008-05-19

申请人： Kong-Soo LEE ,  Jae-Jong HAN ,  Sang-Jin PARK ,  Seok-Jae KIM ,  Yong-Woo HYUNG ,  Young-Sub YOU

发明人： Kong-Soo LEE ,  Jae-Jong HAN ,  Sang-Jin PARK ,  Seok-Jae KIM ,  Yong-Woo HYUNG ,  Young-Sub YOU

IPC分类号： H01L21/3205

CPC分类号： H01L21/76879 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02661 ,  H01L21/28525

摘要： A method of forming an epitaxial silicon structure is disclosed. The method includes performing a first epitaxial growth process using a first source gas including silicon (Si) and hydrogen chloride (HCl) to form a first epitaxial silicon layer on a substrate, and performing a second epitaxial growth process using a second source gas including silicon (Si) and chlorine (Cl) to form a second epitaxial silicon layer on the first epitaxial silicon layer.

摘要翻译： 公开了一种形成外延硅结构的方法。 该方法包括使用包括硅（Si）和氯化氢（HCl）的第一源气体进行第一外延生长工艺，以在衬底上形成第一外延硅层，以及使用包括硅的第二源气体进行第二外延生长工艺 （Si）和氯（Cl），以在第一外延硅层上形成第二外延硅层。

公开(公告)号：US20070022941A1

公开(公告)日：2007-02-01

申请号：US11494566

申请日：2006-07-28

申请人： Jae-Young Park ,  Young-Jin Kim ,  Yong-Woo Hyung ,  Seok-Woo Nam ,  Kyoung-Seok Kim ,  Wook-Yeol Yi ,  Hun-Hyeoung Leam ,  Kong-Soo Lee ,  Ko-Eun Lee

发明人： Jae-Young Park ,  Young-Jin Kim ,  Yong-Woo Hyung ,  Seok-Woo Nam ,  Kyoung-Seok Kim ,  Wook-Yeol Yi ,  Hun-Hyeoung Leam ,  Kong-Soo Lee ,  Ko-Eun Lee

IPC分类号： C30B15/14

CPC分类号： C30B29/06 ,  C30B1/023

摘要： In a method of forming a layer having a lower electrical resistance and a method of manufacturing a semiconductor device, a first layer may be formed on a single crystalline substrate using amorphous silicon doped with impurities. A heat treatment may be performed on the single crystalline substrate at a temperature of about 550° C. to about 600° C. to convert the first layer into a second layer including a single crystalline silicon film transformed from a lower portion of the first layer contacting the single crystalline substrate and a polysilicon film transformed from an upper portion of the first layer. The layer may be formed at a relatively low temperature by a selective epitaxial growth process, and thus degradation or damage to a semiconductor device, which may be generated in a high temperature process, may be reduced.

摘要翻译： 在形成具有较低电阻的层的方法和制造半导体器件的方法中，可以使用掺杂有杂质的非晶硅在单晶衬底上形成第一层。 可以在约550℃至约600℃的温度下对单晶衬底进行热处理，以将第一层转变成第二层，该第二层包括从第一层的下部变换的单晶硅膜 使所述单晶衬底和从所述第一层的上部变换的多晶硅膜接触。 可以通过选择性外延生长工艺在相对低的温度下形成该层，从而可以降低在高温过程中可能产生的对半导体器件的劣化或损坏。

公开(公告)号：US06794263B1

公开(公告)日：2004-09-21

申请号：US10367931

申请日：2003-02-19

申请人： Kong-Soo Lee ,  Young-Wook Park ,  Jae-Jong Han ,  Gi-Hyun Hwang ,  Kyoung-Seok Kim ,  Sung-Eui Kim ,  Seung-Mok Shin

发明人： Kong-Soo Lee ,  Young-Wook Park ,  Jae-Jong Han ,  Gi-Hyun Hwang ,  Kyoung-Seok Kim ,  Sung-Eui Kim ,  Seung-Mok Shin

IPC分类号： H01L2176

CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/76229 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/959 ,  Y10S438/975 ,  H01L2924/00

摘要： A method of inhibiting pit occurrence on a semiconductor substrate during manufacture of a semiconductor device includes forming an isolation using a shallow trench isolation (STI) method in a semiconductor substrate, forming an insulation layer on an entire surface of the semiconductor substrate having the isolation, implanting ions into the semiconductor substrate using the insulation layer as a buffer layer, annealing the semiconductor substrate using a rapid thermal annealing (RTA) process, forming a photoresist layer on the insulation layer and then forming an opening in the photoresist layer to expose an underlayer thereof, forming an align key by etching the underlayer at the opening, and removing the photoresist layer and the insulation layer. Alternatively, the thickness of the insulation layer may be reduced to prevent the occurrence of pits on active areas of the semiconductor substrate.

摘要翻译： 在半导体器件的制造期间抑制半导体衬底上的凹坑产生的方法包括在半导体衬底中形成使用浅沟槽隔离（STI）方法的隔离，在具有隔离的半导体衬底的整个表面上形成绝缘层， 使用绝缘层作为缓冲层将离子注入到半导体衬底中，使用快速热退火（RTA）工艺对半导体衬底进行退火，在绝缘层上形成光致抗蚀剂层，然后在光刻胶层中形成开口以暴露底层 通过在开口处蚀刻底层形成对准键，以及去除光致抗蚀剂层和绝缘层。 或者，可以减小绝缘层的厚度，以防止在半导体衬底的有源区域上出现凹坑。

公开(公告)号：US08329539B2

公开(公告)日：2012-12-11

申请号：US11429890

申请日：2006-05-08

申请人： Dae-Won Ha ,  Kong-Soo Lee ,  Sung-Sam Lee ,  Sang-Hyun Lee ,  Min-Young Shim

发明人： Dae-Won Ha ,  Kong-Soo Lee ,  Sung-Sam Lee ,  Sang-Hyun Lee ,  Min-Young Shim

IPC分类号： H01L21/336 ,  H01L21/8242

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66628 ,  H01L29/7834

摘要： In a semiconductor device having a recessed gate electrode and a method of fabricating the same, a channel trench is formed in a semiconductor substrate by etching the semiconductor substrate. A first semiconductor layer is formed on the semiconductor substrate that fills the channel trench. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer having a lower impurity concentration than the first semiconductor layer.

摘要翻译： 在具有凹陷栅电极的半导体器件及其制造方法中，通过蚀刻半导体衬底在半导体衬底中形成沟槽。 在半导体衬底上形成填充沟槽的第一半导体层。 第二半导体层形成在第一半导体层上，第二半导体层的杂质浓度低于第一半导体层。

公开(公告)号：US08119503B2

公开(公告)日：2012-02-21

申请号：US12498528

申请日：2009-07-07

申请人： Kong-Soo Lee ,  Kyoung-Seok Kim ,  Sang-Jin Park ,  Chang-Hoon Lee ,  Ji-Hyun Jeong ,  Jae-Hyun Park ,  Jae-Hee Oh

发明人： Kong-Soo Lee ,  Kyoung-Seok Kim ,  Sang-Jin Park ,  Chang-Hoon Lee ,  Ji-Hyun Jeong ,  Jae-Hyun Park ,  Jae-Hee Oh

IPC分类号： H01L47/00 ,  H01L21/20

CPC分类号： H01L27/1021 ,  H01L27/24 ,  H01L29/8613

摘要： Methods of forming integrated circuit devices include forming an etch stop layer on a surface of a semiconductor substrate and forming a first interlayer insulating layer on the etch stop layer. The first interlayer insulating layer is patterned to define an opening therein that exposes a first portion of the etch stop layer. This first portion of the etch stop layer is then removed to thereby expose an underlying portion of the surface of the semiconductor substrate. This removal of the etch stop layer may be performed by wet etching the first portion of the etch stop layer using a phosphoric acid solution. A semiconductor region is then selectively grown into the opening, using the exposed portion of the surface of the semiconductor substrate as an epitaxial seed layer.

摘要翻译： 形成集成电路器件的方法包括在半导体衬底的表面上形成蚀刻停止层，并在蚀刻停止层上形成第一层间绝缘层。 图案化第一层间绝缘层以限定其中暴露出蚀刻停止层的第一部分的开口。 然后去除蚀刻停止层的第一部分，从而暴露半导体衬底的表面的下面部分。 蚀刻停止层的这种去除可以通过使用磷酸溶液湿蚀刻蚀刻停止层的第一部分来进行。 然后使用半导体衬底的表面的暴露部分作为外延种子层，选择性地将半导体区域生长到开口中。