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    Stacked semiconductor devices and methods of manufacturing the same
    1.
    发明申请
    Stacked semiconductor devices and methods of manufacturing the same 失效
    叠层半导体器件及其制造方法

    公开(公告)号：US20080023770A1

    公开(公告)日：2008-01-31

    申请号：US11823765

    申请日：2007-06-28

    申请人： Kyoung-Seok Kim ,  Kong-Soo Lee ,  Sang-Jin Park ,  Sung-Kwan Kang ,  Ko-Eun Lee

    发明人： Kyoung-Seok Kim ,  Kong-Soo Lee ,  Sang-Jin Park ,  Sung-Kwan Kang ,  Ko-Eun Lee

    IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L23/58

    CPC分类号： H01L27/0688 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28556 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/8221 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108

    摘要： The stacked semiconductor device includes a semiconductor substrate, a multi-layered insulation layer pattern having at least two insulation layer patterns and an opening, an active layer pattern formed on each of the insulation layer patterns, a first plug including single crystalline silicon-germanium, a second plug including single crystalline silicon, and a wiring electrically connected to the first plug and sufficiently filling up the opening. The insulation layer patterns are vertically stacked on the semiconductor substrate and the opening exposes an upper face of the semiconductor substrate. A side portion of the active layer pattern is exposed by the opening. The first plug is formed on the upper face of the semiconductor substrate to partially fill the opening. The second plug is partially formed on the first plug, and has substantially the same interface as that of the first plug.

    摘要翻译： 叠层半导体器件包括半导体衬底，具有至少两个绝缘层图案和开口的多层绝缘层图案，形成在每个绝缘层图案上的有源层图案，包括单晶硅锗的第一插头， 包括单晶硅的第二插头和电连接到第一插头并充分填满开口的布线。 绝缘层图案垂直堆叠在半导体衬底上，并且开口暴露半导体衬底的上表面。 有源层图案的侧面部分由开口露出。 第一插头形成在半导体衬底的上表面上以部分地填充开口。 第二插头部分地形成在第一插头上，并且具有与第一插头基本相同的界面。

    Method of forming a layer and method of manufacturing a semiconductor device using the same
    2.
    发明申请
    Method of forming a layer and method of manufacturing a semiconductor device using the same 审中-公开
    形成层的方法和使用其制造半导体器件的方法

    公开(公告)号：US20070022941A1

    公开(公告)日：2007-02-01

    申请号：US11494566

    申请日：2006-07-28

    申请人： Jae-Young Park ,  Young-Jin Kim ,  Yong-Woo Hyung ,  Seok-Woo Nam ,  Kyoung-Seok Kim ,  Wook-Yeol Yi ,  Hun-Hyeoung Leam ,  Kong-Soo Lee ,  Ko-Eun Lee

    发明人： Jae-Young Park ,  Young-Jin Kim ,  Yong-Woo Hyung ,  Seok-Woo Nam ,  Kyoung-Seok Kim ,  Wook-Yeol Yi ,  Hun-Hyeoung Leam ,  Kong-Soo Lee ,  Ko-Eun Lee

    IPC分类号： C30B15/14

    CPC分类号： C30B29/06 ,  C30B1/023

    摘要： In a method of forming a layer having a lower electrical resistance and a method of manufacturing a semiconductor device, a first layer may be formed on a single crystalline substrate using amorphous silicon doped with impurities. A heat treatment may be performed on the single crystalline substrate at a temperature of about 550° C. to about 600° C. to convert the first layer into a second layer including a single crystalline silicon film transformed from a lower portion of the first layer contacting the single crystalline substrate and a polysilicon film transformed from an upper portion of the first layer. The layer may be formed at a relatively low temperature by a selective epitaxial growth process, and thus degradation or damage to a semiconductor device, which may be generated in a high temperature process, may be reduced.

    摘要翻译： 在形成具有较低电阻的层的方法和制造半导体器件的方法中，可以使用掺杂有杂质的非晶硅在单晶衬底上形成第一层。 可以在约550℃至约600℃的温度下对单晶衬底进行热处理，以将第一层转变成第二层，该第二层包括从第一层的下部变换的单晶硅膜 使所述单晶衬底和从所述第一层的上部变换的多晶硅膜接触。 可以通过选择性外延生长工艺在相对低的温度下形成该层，从而可以降低在高温过程中可能产生的对半导体器件的劣化或损坏。

    Stacked semiconductor devices and methods of manufacturing the same
    4.
    发明授权
    Stacked semiconductor devices and methods of manufacturing the same 失效
    叠层半导体器件及其制造方法

    公开(公告)号：US08039900B2

    公开(公告)日：2011-10-18

    申请号：US11823765

    申请日：2007-06-28

    申请人： Kyoung-Seok Kim ,  Kong-Soo Lee ,  Sang-Jin Park ,  Sung-Kwan Kang ,  Ko-Eun Lee

    发明人： Kyoung-Seok Kim ,  Kong-Soo Lee ,  Sang-Jin Park ,  Sung-Kwan Kang ,  Ko-Eun Lee

    IPC分类号： H01L29/66

    CPC分类号： H01L27/0688 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28556 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/8221 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108

    摘要： The stacked semiconductor device includes a semiconductor substrate, a multi-layered insulation layer pattern having at least two insulation layer patterns and an opening, an active layer pattern formed on each of the insulation layer patterns, a first plug including single crystalline silicon-germanium, a second plug including single crystalline silicon, and a wiring electrically connected to the first plug and sufficiently filling up the opening. The insulation layer patterns are vertically stacked on the semiconductor substrate and the opening exposes an upper face of the semiconductor substrate. A side portion of the active layer pattern is exposed by the opening. The first plug is formed on the upper face of the semiconductor substrate to partially fill the opening. The second plug is partially formed on the first plug, and has substantially the same interface as that of the first plug.

    摘要翻译： 叠层半导体器件包括半导体衬底，具有至少两个绝缘层图案和开口的多层绝缘层图案，形成在每个绝缘层图案上的有源层图案，包括单晶硅锗的第一插头， 包括单晶硅的第二插头和电连接到第一插头并充分填满开口的布线。 绝缘层图案垂直堆叠在半导体衬底上，并且开口暴露半导体衬底的上表面。 有源层图案的侧面部分由开口露出。 第一插头形成在半导体衬底的上表面上以部分地填充开口。 第二插头部分地形成在第一插头上，并且具有与第一插头基本相同的界面。