公开(公告)号：US20160086943A1

公开(公告)日：2016-03-24

申请号：US14857135

申请日：2015-09-17

申请人： Sun Young LEE ,  Jae Young Park ,  Han Ki Lee ,  Bon Young Koo ,  Hong Bum Park ,  Young Su Chung ,  Jae Jong Han

发明人： Sun Young LEE ,  Jae Young Park ,  Han Ki Lee ,  Bon Young Koo ,  Hong Bum Park ,  Young Su Chung ,  Jae Jong Han

IPC分类号： H01L27/088 ,  H01L29/423 ,  H01L29/06

CPC分类号： H01L29/42368 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/302 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L29/165 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7854

摘要： A semiconductor device includes a substrate, an isolation layer on the substrate, and at least one active fin on the substrate. The isolation layer includes a first surface opposite a second surface. The first surface is contiguous with the substrate. The at least one active fin protrudes from the substrate and includes a first region having a side wall above the second surface of the isolation layer and a second region on the first region. The second region has an upper surface. The first region has a first width contiguous with the second surface of the isolation layer and a second width contiguous with the second region. The second width is 60% or greater than the first width (e.g., 60% to 100%).

摘要翻译： 半导体器件包括衬底，衬底上的隔离层以及衬底上的至少一个活性鳍。 隔离层包括与第二表面相对的第一表面。 第一表面与基底相邻。 所述至少一个活性翅片从所述基底突出并且包括具有位于所述隔离层的第二表面上方的侧壁的第一区域和所述第一区域上的第二区域。 第二区域具有上表面。 第一区域具有与隔离层的第二表面邻接的第一宽度和与第二区域相邻的第二宽度。 第二宽度为第一宽度（例如，60％至100％）的60％或更大。

公开(公告)号：US08241979B2

公开(公告)日：2012-08-14

申请号：US12805825

申请日：2010-08-20

申请人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

发明人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

IPC分类号： H01L21/8234

CPC分类号： H01L45/143 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02672 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/66136 ,  H01L29/66204 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.

摘要翻译： 形成垂直二极管的方法和制造半导体器件（例如，诸如相变存储器件的半导体存储器件）的方法包括：在衬底上形成具有开口的绝缘结构，并用非晶硅填充该开口 层。 形成金属硅化物层以接触非晶硅层的至少一部分，然后通过使用金属硅化物层使非晶硅层结晶而在开口中形成多晶硅层。 通过将杂质注入到多晶硅层中形成掺杂多晶硅层。 因此，在开口中形成多晶硅层，而不进行选择性外延生长（SEG）工艺，从而可以提高二极管的电特性。

公开(公告)号：US20090108323A1

公开(公告)日：2009-04-30

申请号：US12228772

申请日：2008-08-15

申请人： Jung-Geun Jee ,  Ho-Min Son ,  Yong-Woo Hyung ,  Jae-Jong Han ,  Taek-Jin Lim

发明人： Jung-Geun Jee ,  Ho-Min Son ,  Yong-Woo Hyung ,  Jae-Jong Han ,  Taek-Jin Lim

IPC分类号： H01L29/788 ,  H01L21/3215 ,  H01L21/22

CPC分类号： H01L29/42324 ,  H01L21/76224 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7887

摘要： A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.

摘要翻译： 提供一种制造非易失性存储器件的方法。 该方法包括形成在衬底上限定有源区的隔离图案，在有源区上形成浮置栅极图案，以及在浮栅图案上形成栅极线。 浮置栅极图案在有源区域上是自对准的，并且当浮栅图案更靠近有源区域时，其杂质离子浓度变得相对较低。

公开(公告)号：US20080200014A1

公开(公告)日：2008-08-21

申请号：US12034440

申请日：2008-02-20

申请人： Sang-Jin PARK ,  Kong-Soo LEE ,  Yong-Woo HYUNG ,  Young-Sub YOU ,  Jae-Jong HAN

发明人： Sang-Jin PARK ,  Kong-Soo LEE ,  Yong-Woo HYUNG ,  Young-Sub YOU ,  Jae-Jong HAN

IPC分类号： H01L21/36

CPC分类号： H01L45/143 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02672 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/66136 ,  H01L29/66204 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.

摘要翻译： 形成垂直二极管的方法和制造半导体器件（例如，诸如相变存储器件的半导体存储器件）的方法包括：在衬底上形成具有开口的绝缘结构，并用非晶硅填充该开口 层。 形成金属硅化物层以接触非晶硅层的至少一部分，然后通过使用金属硅化物层使非晶硅层结晶而在开口中形成多晶硅层。 通过将杂质注入到多晶硅层中形成掺杂多晶硅层。 因此，在开口中形成多晶硅层，而不进行选择性外延生长（SEG）工艺，从而可以提高二极管的电特性。

公开(公告)号：US20080029031A1

公开(公告)日：2008-02-07

申请号：US11838998

申请日：2007-08-15

申请人： Jae-Hyun Yeo ,  Young-Wook Park ,  Ki-Chul Kim ,  Jae-Jong Han

发明人： Jae-Hyun Yeo ,  Young-Wook Park ,  Ki-Chul Kim ,  Jae-Jong Han

IPC分类号： C23C16/54

CPC分类号： C23C16/44 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691

摘要： Methods and apparatus are provided for forming thin films for semiconductor devices, which enable supplying and removing reactants containing constituent elements of a thin film to be formed, by preheating and supplying a process gas and a purging gas at a predetermined temperature in forming the thin film on a substrate. For example, a method for forming a thin film includes supplying a first reactant to a chamber to chemically absorb the first reactant onto a substrate, the first reactant being bubbled by a first gas that is preheated, purging the chamber to remove residues on the substrate having the first reactant chemically absorbed, and forming the thin film by a means of chemical displacement by supplying a second reactant to the chamber to chemically absorb the second reactant onto the substrate.

摘要翻译： 提供了用于形成用于半导体器件的薄膜的方法和装置，其能够通过在预定温度下预热和提供处理气体和净化气体来形成薄膜来提供和除去含有待形成的薄膜的构成元素的反应物 在基板上。 例如，形成薄膜的方法包括将第一反应物供应到室以将第一反应物化学吸收到基底上，第一反应物被预热的第一气体鼓泡，清洗室以除去基底上的残留物 使所述第一反应物被化学吸收，并且通过向所述室供应第二反应物以化学吸收所述第二反应物到所述衬底上，通过化学位移形成所述薄膜。

公开(公告)号：US20050022741A1

公开(公告)日：2005-02-03

申请号：US10890959

申请日：2004-07-12

申请人： Jung-Hun Seo ,  Young-Wook Park ,  Jae-Jong Han

发明人： Jung-Hun Seo ,  Young-Wook Park ,  Jae-Jong Han

IPC分类号： H01L21/205 ,  C23C16/00 ,  C23C16/02 ,  C23C16/06 ,  C23C16/458 ,  C23C16/46 ,  H01L21/285 ,  H01L21/3205

CPC分类号： H01L21/32051 ,  C23C16/0272 ,  C23C16/06 ,  C23C16/4586 ,  C23C16/46 ,  C23C16/466 ,  H01L21/28556

摘要： In one embodiment, a chemical vapor deposition (CVD) apparatus comprising a plurality of backside gas (BSG) passages that pass through a heater table that controls a temperature of a plurality of local areas on a wafer and a method of forming a thin layer using the CVD apparatus are provided. The heater table comprises a wafer supporting area divided into a plurality of local areas that correspond to the local areas of the wafer. Each of the BSG passages has a BSG outlet that supplies the BSG, heated by a heater, to the local areas. Flow controllers control the flow through each of the BSG passages, thereby controlling the temperature of local areas.

摘要翻译： 在一个实施方案中，化学气相沉积（CVD）装置包括多个背面气体（BSG）通道，其通过加热台，该加热器台控制晶片上的多个局部区域的温度，以及使用 提供CVD装置。 加热器台包括分为对应于晶片的局部区域的多个局部区域的晶片支撑区域。 每个BSG通道具有BSG出口，其将由加热器加热的BSG供应到局部区域。 流量控制器控制通过每个BSG通道的流量，从而控制局部区域的温度。

公开(公告)号：US06730570B2

公开(公告)日：2004-05-04

申请号：US10348017

申请日：2003-01-22

申请人： Seung-Mok Shin ,  Jae-Jong Han ,  Ki-Hyun Hwang

发明人： Seung-Mok Shin ,  Jae-Jong Han ,  Ki-Hyun Hwang

IPC分类号： H01L21336

CPC分类号： H01L21/76897 ,  H01L21/76831 ,  H01L29/6656

摘要： A method for forming a self-aligned contact in a semiconductor device which can reduce process failures and a method for manufacturing a semiconductor device that includes the self-aligned contact are provided. A self-aligned contact hole is formed in an interlayer dielectric film to expose a portion of the substrate between conductive structures formed thereon. A buffer layer is formed on a sidewall of the self-aligned contact hole, on the bottom of the self-aligned contact hole, and on the interlayer dielectric film such that the thickness of the buffer layer at an upper portion of the self-aligned contact hole is greater than the thickness of the buffer layer at the bottom of the self-aligned contact hole. After removing the portion of the buffer layer on the bottom of the self-aligned contact hole, a contact is formed in the self-aligned contact hole to make contact with the substrate.

摘要翻译： 提供了一种用于在可以减少工艺故障的半导体器件中形成自对准接触的方法以及包括自对准接触的半导体器件的制造方法。 在层间电介质膜中形成自对准接触孔，以在其上形成的导电结构之间露出基板的一部分。 在自对准接触孔的侧壁，自对准接触孔的底部和层间电介质膜上形成缓冲层，使得缓冲层在自对准的上部的厚度 接触孔大于自对准接触孔底部缓冲层的厚度。 在自对准接触孔的底部上移除缓冲层的部分之后，在自对准接触孔中形成接触以与衬底接触。

公开(公告)号：US20100323489A1

公开(公告)日：2010-12-23

申请号：US12805825

申请日：2010-08-20

申请人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

发明人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

IPC分类号： H01L21/02

CPC分类号： H01L45/143 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02672 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/66136 ,  H01L29/66204 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.

公开(公告)号：US06723662B2

公开(公告)日：2004-04-20

申请号：US10630101

申请日：2003-07-30

申请人： Kong-soo Lee ,  Jae-jong Han ,  Sung-eui Kim

发明人： Kong-soo Lee ,  Jae-jong Han ,  Sung-eui Kim

IPC分类号： H01L218242

CPC分类号： H01L21/28185 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/10894 ,  H01L27/11

摘要： Methods of forming gate oxide films in integrated circuit devices using wet or dry oxidization processes with a reduced amount of chloride are disclosed. A gate oxide film is formed on a substrate on an active region adjacent to a trench isolation region in a first gas atmosphere with a first amount of chloride. The gate oxide film is annealed in a second gas atmosphere including a second amount of chloride that is greater than the first amount.

摘要翻译： 公开了使用具有减少量的氯化物的湿式或干式氧化方法在集成电路器件中形成栅极氧化膜的方法。 在具有第一量氯化物的第一气体气氛中的与沟槽隔离区相邻的有源区上的衬底上形成栅极氧化膜。 栅极氧化膜在包括大于第一量的第二量氯化物的第二气体气氛中退火。

公开(公告)号：US20160293705A1

公开(公告)日：2016-10-06

申请号：US14977865

申请日：2015-12-22

申请人： Han-ki Lee ,  Jae-Young Park ,  Dong-Hun Lee ,  Bon-Young Koo ,  Sun-Young Lee ,  Jae-Jong Han

发明人： Han-ki Lee ,  Jae-Young Park ,  Dong-Hun Lee ,  Bon-Young Koo ,  Sun-Young Lee ,  Jae-Jong Han

IPC分类号： H01L29/10 ,  H01L29/786 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/1054 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a multi-channel active pattern including germanium and an inner region and an outer region, the outer region formed along a profile of the inner region, and a germanium fraction of the outer region being smaller than a germanium fraction of the inner region. A gate electrode intersects the multi-channel active pattern.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括包括锗和内部区域以及外部区域的多通道活性图案，沿着内部区域的轮廓形成外部区域，并且外部区域的锗部分小于内部区域的锗部分 地区。 栅电极与多通道有源图案相交。