公开(公告)号：US08546872B2

公开(公告)日：2013-10-01

申请号：US13072366

申请日：2011-03-25

Applicant: Kiwamu Sakuma ,  Atsuhiro Kinoshita

Inventor： Kiwamu Sakuma ,  Atsuhiro Kinoshita

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/7881

Abstract: According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other.

Abstract translation: 根据一个实施例，存储器件包括半导体衬底，第一，第二，第三和第四鳍式堆叠层结构，每个具有堆叠在垂直于半导体衬底的表面的第一方向上的存储串，并且每个延伸到 第二方向平行于半导体衬底的表面，第一部分连接到第一和第二鳍式堆叠层的第二方向上的第一端彼此结合，第二部分连接到第三端的第二端 第四鳍状堆叠层结构，第三部分与第一和第三鳍状堆叠层的第二方向的第二端部连接，第四部分与第二鳍片状堆叠层的第二方向的第二端部连接， 第二和第四鳍式堆叠层结构。

公开(公告)号：US20120075928A1

公开(公告)日：2012-03-29

申请号：US13246996

申请日：2011-09-28

Applicant: Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

Inventor： Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

IPC: H01L29/792 ,  G11C11/34 ,  G11C11/412

CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L27/11568 ,  H01L29/4234

Abstract: In a semiconductor layer, information is written by applying a first potential to a first electrode, applying a second potential that is lower than the first potential to all of back gate electrodes, applying a third potential that is higher than the first potential to the first to (i−1)th front gate electrodes, and applying a fourth potential that is between the second and third potentials to the ith and subsequent front gate electrodes, where “i” is a positive integer and identifies a specific location to which information is to be written.

Abstract translation: 在半导体层中，通过向第一电极施加第一电位，向所有背栅电极施加低于第一电位的第二电位，向第一电极施加高于第一电位的第三电位，写入信息 到（i-1）个前栅电极，并且将第二和第三电位之间的第四电位施加到第i个和后续的前栅电极，其中“i”是正整数，并且识别信息的特定位置 要写

公开(公告)号：US20120068241A1

公开(公告)日：2012-03-22

申请号：US13236734

申请日：2011-09-20

Applicant: Kiwamu SAKUMA ,  Atsuhiro KINOSHITA

Inventor： Kiwamu SAKUMA ,  Atsuhiro KINOSHITA

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L27/11578 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L29/785 ,  H01L29/792

Abstract: According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.

Abstract translation: 根据一个实施例，存储器件包括第一和第二鳍式堆叠结构，每个第一和第二鳍式堆叠结构每个包括沿第一方向堆叠的第一至第i存储器串（i是除1之外的自然数），第一和第二鳍式堆叠结构 其在第二方向上延伸并且在第三方向上相邻，第一部分连接到第一鳍式堆叠结构的第二方向上的一端，第一部分的第三方向上的宽度大于第一方向上的宽度 第一鳍式堆叠结构的第三方向和与第二鳍式堆叠结构的第二方向的一端连接的第二部分，第二部分的第三方向上的宽度大于第三方向上的宽度 的第二鳍式堆叠结构。

公开(公告)号：US07749919B2

公开(公告)日：2010-07-06

申请号：US11896860

申请日：2007-09-06

Applicant: Kiwamu Sakuma ,  Daisuke Matsushita ,  Koichi Kato ,  Yasushi Nakasaki ,  Izumi Hirano ,  Kouichi Muraoka ,  Yuichiro Mitani ,  Shigeto Fukatsu ,  Toshihide Ito

Inventor： Kiwamu Sakuma ,  Daisuke Matsushita ,  Koichi Kato ,  Yasushi Nakasaki ,  Izumi Hirano ,  Kouichi Muraoka ,  Yuichiro Mitani ,  Shigeto Fukatsu ,  Toshihide Ito

IPC: H01L21/321

CPC classification number: H01L21/28273

Abstract: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region; a charge storage film formed on the first insulating film; a second insulating film formed above the charge storage film and made of a high-permittivity material; a control gate electrode formed above the second insulating film; and a silicon nitride layer including nitrogen atoms having three-coordinate nitrogen bonds, at least one of second-nearest neighbor atoms of the nitrogen atoms being a nitrogen atom. At least one of the charge storage film and the control gate electrode contains silicon, the silicon nitride layer is located between the second insulating film and the at least one of the charge storage film and the control gate electrode.

Abstract translation: 半导体器件包括：半导体衬底; 在半导体衬底中形成为彼此间隔一定距离的源极区域和漏极区域; 形成在半导体衬底的一部分上的第一绝缘膜，该部分位于源区和漏区之间; 形成在所述第一绝缘膜上的电荷存储膜; 形成在电荷存储膜上方并由高介电常数材料制成的第二绝缘膜; 形成在所述第二绝缘膜上方的控制栅电极; 和包含具有三配位氮键的氮原子的氮化硅层，氮原子的第二最近邻原子中的至少一个为氮原子。 电荷存储膜和控制栅电极中的至少一个包含硅，氮化硅层位于第二绝缘膜和电荷存储膜和控制栅电极中的至少一个之间。

公开(公告)号：US08829594B2

公开(公告)日：2014-09-09

申请号：US13469867

申请日：2012-05-11

Applicant: Kosuke Tatsumura ,  Kiwamu Sakuma ,  Koichiro Zaitsu ,  Mari Matsumoto

Inventor： Kosuke Tatsumura ,  Kiwamu Sakuma ,  Koichiro Zaitsu ,  Mari Matsumoto

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0441 ,  H01L27/11568 ,  H01L29/66833

Abstract: A nonvolatile programmable switch according to an embodiment includes: a first nonvolatile memory transistor including a first to third terminals connected to a first to third interconnects respectively; a second nonvolatile memory transistor including a fourth terminal connected to a fourth interconnect, a fifth terminal connected to the second interconnect, and a sixth terminal connected to the third interconnect, the first and second nonvolatile memory transistors having the same conductivity type; and a pass transistor having a gate electrode connected to the second interconnect. When the first and fourth interconnects are connected to a first power supply while the third interconnect is connected to a second power supply having a higher voltage than that of the first power supply, a threshold voltage of the first nonvolatile memory transistor increases, and a threshold voltage of the second nonvolatile memory transistor decreases.

Abstract translation: 根据实施例的非易失性可编程开关包括：第一非易失性存储晶体管，包括分别连接到第一至第三互连的第一至第三端子; 第二非易失性存储晶体管，包括连接到第四互连的第四端子，连接到第二互连的第五端子和连接到第三互连件的第六端子，具有相同导电类型的第一和第二非易失性存储器晶体管; 以及具有连接到第二互连的栅电极的传输晶体管。 当第一和第四互连连接到第一电源，而第三互连连接到具有比第一电源的电压更高的电压的第二电源时，第一非易失性存储晶体管的阈值电压增加，阈值 第二非易失性存储晶体管的电压降低。

公开(公告)号：US20130175490A1

公开(公告)日：2013-07-11

申请号：US13547645

申请日：2012-07-12

Applicant: Haruka KUSAI ,  Kiwamu Sakuma ,  Shosuke Fujii ,  Masumi Saitoh ,  Masahiro Kiyotoshi

Inventor： Haruka KUSAI ,  Kiwamu Sakuma ,  Shosuke Fujii ,  Masumi Saitoh ,  Masahiro Kiyotoshi

IPC: H01L27/088 ,  H01L27/24 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L27/088 ,  G11C16/04 ,  G11C16/10 ,  H01L21/02367 ,  H01L21/265 ,  H01L21/32051 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/24 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/685 ,  H01L29/788 ,  H01L29/792 ,  H01L29/82

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.

Abstract translation: 根据一个实施例，非易失性半导体存储器件包括具有存储单元的鳍式堆叠层结构和连接到该结构的端部的光束。 结构和梁中的每一个包括沿垂直方向堆叠的半导体层。 梁包括设置在梁的一端的接触部分和设置在接触部分和结构的端部之间的低电阻部分。

公开(公告)号：US08467241B2

公开(公告)日：2013-06-18

申请号：US13246996

申请日：2011-09-28

Applicant: Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

Inventor： Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

IPC: G11C11/34

CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L27/11568 ,  H01L29/4234

Abstract: In a semiconductor layer, information is written by applying a first potential to a first electrode, applying a second potential that is lower than the first potential to all of back gate electrodes, applying a third potential that is higher than the first potential to the first to (i−1)th front gate electrodes, and applying a fourth potential that is between the second and third potentials to the ith and subsequent front gate electrodes, where “i” is a positive integer and identifies a specific location to which information is to be written.

Abstract translation: 在半导体层中，通过向第一电极施加第一电位，向所有背栅电极施加低于第一电位的第二电位，向第一电极施加高于第一电位的第三电位，写入信息 到（i-1）个前栅电极，并且将第二和第三电位之间的第四电位施加到第i个和后续的前栅电极，其中“i”是正整数，并且识别信息的特定位置 要写

公开(公告)号：US20130134499A1

公开(公告)日：2013-05-30

申请号：US13469867

申请日：2012-05-11

Applicant: Kosuke TATSUMURA ,  Kiwamu Sakuma ,  Koichiro Zaitsu ,  Mari Matsumoto

Inventor： Kosuke TATSUMURA ,  Kiwamu Sakuma ,  Koichiro Zaitsu ,  Mari Matsumoto

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0441 ,  H01L27/11568 ,  H01L29/66833

Abstract: A nonvolatile programmable switch according to an embodiment includes: a first nonvolatile memory transistor including a first to third terminals connected to a first to third interconnects respectively; a second nonvolatile memory transistor including a fourth terminal connected to a fourth interconnect, a fifth terminal connected to the second interconnect, and a sixth terminal connected to the third interconnect, the first and second nonvolatile memory transistors having the same conductivity type; and a pass transistor having a gate electrode connected to the second interconnect. When the first and fourth interconnects are connected to a first power supply while the third interconnect is connected to a second power supply having a higher voltage than that of the first power supply, a threshold voltage of the first nonvolatile memory transistor increases, and a threshold voltage of the second nonvolatile memory transistor decreases.

Abstract translation: 根据实施例的非易失性可编程开关包括：第一非易失性存储晶体管，包括分别连接到第一至第三互连的第一至第三端子; 第二非易失性存储晶体管，包括连接到第四互连的第四端子，连接到第二互连的第五端子和连接到第三互连件的第六端子，具有相同导电类型的第一和第二非易失性存储器晶体管; 以及具有连接到第二互连的栅电极的传输晶体管。 当第一和第四互连连接到第一电源，而第三互连连接到具有比第一电源的电压更高的电压的第二电源时，第一非易失性存储晶体管的阈值电压增加，阈值 第二非易失性存储晶体管的电压降低。

公开(公告)号：US20130015520A1

公开(公告)日：2013-01-17

申请号：US13622644

申请日：2012-09-19

Applicant: Fujii Shosuke ,  Daisuke Nagishima ,  Kiwamu Sakuma

Inventor： Fujii Shosuke ,  Daisuke Nagishima ,  Kiwamu Sakuma

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11578 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/11568

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure in which a first insulating layer, a first semiconductor layer, . . . an n-th insulating layer, an n-th semiconductor layer, and an (n+1)-th insulating layer (n is a natural number equal to or more than 2) are stacked in order thereof in a first direction perpendicular to a surface of a semiconductor substrate and which extends in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory strings which use the first to n-th semiconductor layers as channels respectively, a common semiconductor layer which combines the first to n-th semiconductor layers at first ends of the first to n-th memory strings in the second direction.

Abstract translation: 根据一个实施例，非易失性半导体存储器件包括翅片型堆叠层结构，其中第一绝缘层，第一半导体层， 。 。 第n绝缘层，第n半导体层和第（n + 1）绝缘层（n是等于或大于2的自然数）按照与第一绝缘层垂直的第一方向的顺序堆叠 半导体衬底的表面，并且在平行于半导体衬底的表面的第二方向上延伸，分别使用第一至第n半导体层作为沟道的第一至第n存储器串，共同的半导体层，其组合第一 在第二方向上的第一至第n存储器串的第一端处的n个半导体层。

公开(公告)号：US20130015519A1

公开(公告)日：2013-01-17

申请号：US13622612

申请日：2012-09-19

Applicant: Shosuke Fujii ,  Kiwamu Sakuma ,  Jun Fujiki ,  Atsuhiro Kinoshita

Inventor： Shosuke Fujii ,  Kiwamu Sakuma ,  Jun Fujiki ,  Atsuhiro Kinoshita

IPC: H01L29/792 ,  H01L21/28

CPC classification number: H01L27/11551 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11578

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first to n-th semiconductor layers which are stacked in a first direction perpendicular to a surface of a semiconductor substrate and which extend in a second direction parallel to the surface of the semiconductor substrate, an electrode which extends in the first direction along side surfaces of the first to n-th semiconductor layers, the side surfaces of the first to n-th semiconductor layers exposing in a third direction perpendicular to the first and second directions, and first to n-th charge storage layers located between the first to n-th semiconductor layers and the electrode respectively. The first to n-th charge storage layers are separated from each other in areas between the first to n-th semiconductor layers.

Abstract translation: 根据一个实施例，非易失性半导体存储器件包括第一至第n半导体层，它们沿垂直于半导体衬底的表面的第一方向堆叠并且沿与半导体衬底的表面平行的第二方向延伸， 电极，其沿第一方向沿着第一至第n半导体层的侧表面延伸，第一至第n半导体层的侧表面在垂直于第一和第二方向的第三方向上暴露，以及第一至第n- 分别位于第一至第n半导体层之间的电荷存储层和电极。 第一至第n电荷存储层在第一至第n半导体层之间的区域中彼此分离。