公开(公告)号：US08269323B2

公开(公告)日：2012-09-18

申请号：US12557873

申请日：2009-09-11

申请人： Rezaur Rahman Khan ,  Ken Jian Ming Wang

发明人： Rezaur Rahman Khan ,  Ken Jian Ming Wang

IPC分类号： H01L23/495 ,  H01L23/52

CPC分类号： H01L23/49811 ,  H01L21/56 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner. A second integrated circuit package may be mounted to the first package. Signals of the first package may be electrically coupled with the second package at the exposed second ends of the interconnect members. Side surfaces of the interconnect members may be exposed at sides of the first package.

摘要翻译： 提供了用于集成电路封装和封装堆叠的方法，系统和装置。 导电框架附接到基板的第一表面。 导电框架包括周边环部分，多个引线以及定位在由周边环部分形成的周边内的多个互连构件。 每个互连构件通过相应的引线连接到周边环部分。 每个互连构件的第一端耦合到衬底的第一表面。 将封装材料施加到基板的第一表面，而不用封装材料覆盖每个互连构件的第二端。 周界环部分从导电框架移除以隔离多个互连构件。 以这种方式形成第一集成电路封装。 第二集成电路封装可以安装到第一封装。 第一封装的信号可以在互连构件的暴露的第二端处与第二封装电耦合。 互连构件的侧表面可以暴露在第一封装的侧面。

公开(公告)号：US07967184B2

公开(公告)日：2011-06-28

申请号：US11280419

申请日：2005-11-16

申请人： Chih-Chin Liao ,  Ken Jian Ming Wang ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Jack Chang Chien ,  Shrikar Bhagath ,  Cheemen Yu ,  Hem Takiar

发明人： Chih-Chin Liao ,  Ken Jian Ming Wang ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Jack Chang Chien ,  Shrikar Bhagath ,  Cheemen Yu ,  Hem Takiar

IPC分类号： B23K31/02

CPC分类号： H05K1/111 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K3/3421 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09663 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2201/10727 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00014

摘要： A semiconductor package having a low profile is disclosed. In embodiments, a surface mounted component may be mounted directly to the core of the semiconductor package substrate, so that there is no conductive layer, plating layers or solder paste between the component and the substrate core. The surface mounted component may be any type of component which may be surface mounted on a substrate according to an SMT process, including for example passive components and various packaged semiconductors.

摘要翻译： 公开了一种具有低轮廓的半导体封装。 在实施例中，表面安装部件可以直接安装到半导体封装基板的芯部，使得在部件和基板芯之间不存在导电层，镀层或焊膏。 表面安装部件可以是根据SMT工艺可以表面安装在基板上的任何类型的部件，包括例如无源部件和各种封装半导体。

公开(公告)号：US07872335B2

公开(公告)日：2011-01-18

申请号：US11987452

申请日：2007-11-30

申请人： Rezaur Rahman Khan ,  Ken Jian Ming Wang

发明人： Rezaur Rahman Khan ,  Ken Jian Ming Wang

IPC分类号： H01L23/495 ,  H01L23/02

CPC分类号： H01L23/49575 ,  H01L23/3128 ,  H01L23/49503 ,  H01L23/49531 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/20752

摘要： Methods and apparatus for integrated circuit (IC) packages with improved thermal performance and input/output capabilities are described. An integrated circuit (IC) package includes a leadframe, an IC die, a substrate having opposing first and second surfaces, a first wirebond, and a second wirebond. The leadframe includes a die attach pad having opposing first and second surfaces and a plurality of leads that emanate in an outward direction from the die attach pad. The IC die is coupled to the first surface of the die attach pad. The substrate is coupled to the die attach pad. Contact pads on the first surface of the substrate are electrically connected to bond fingers on the second surface of the substrate. The first wirebond couples a first bond pad on a first surface of the IC die to a bond finger on the second surface of the substrate. The second wirebond couples a second bond pad on the first surface of the IC die to a lead of the plurality of leads.

摘要翻译： 描述了具有改进的热性能和输入/输出能力的集成电路（IC）封装的方法和装置。 集成电路（IC）封装包括引线框架，IC管芯，具有相对的第一和第二表面的基板，第一引线键合和第二引线键合。 引线框架包括具有相对的第一和第二表面的管芯附接焊盘和从焊盘附接焊盘向外发出的多个引线。 IC芯片耦合到管芯附接垫的第一表面。 衬底耦合到管芯附接垫。 衬底的第一表面上的接触焊盘电连接到在衬底的第二表面上的接合指状物。 第一引线键将IC管芯的第一表面上的第一接合焊盘与衬底的第二表面上的接合指状物结合。 第二引线键将IC芯片的第一表面上的第二接合焊盘耦合到多个引线的引线。

公开(公告)号：US20090194872A1

公开(公告)日：2009-08-06

申请号：US12023176

申请日：2008-01-31

申请人： Ken Jian Ming Wang ,  Edward Law

发明人： Ken Jian Ming Wang ,  Edward Law

IPC分类号： H01L23/488 ,  B65D85/00 ,  H05K13/04

CPC分类号： H01L21/67333 ,  B65D2585/86 ,  H01L23/49838 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  Y10T29/5313 ,  H01L2924/00 ,  H01L2924/00012

摘要： Methods, systems, and apparatuses for integrated circuit packages, transport containers, and for transporting integrated circuit packages are provided. A transport container for an integrated circuit package includes a body and a plurality of mounting features. The body has a surface that includes a package receiving region. The plurality of mounting features is positioned in the package receiving region. A first mounting feature is positioned on a first inner surface of the package receiving region and a second mounting feature is positioned on a second inner surface of the package receiving region. The package receiving region is configured to receive an integrated circuit package such that the received package is supported by the plurality of mounting features. The first and second mounting features coincide with respective spaces in first and second edges of an array of solder balls on a surface of the package.

摘要翻译： 提供了用于集成电路封装，运输容器和用于运输集成电路封装的方法，系统和装置。 用于集成电路封装的运输容器包括主体和多个安装特征。 主体具有包括包装容纳区域的表面。 多个安装特征位于包装容纳区域中。 第一安装特征位于包装容纳区的第一内表面上，第二安装特征位于包装容纳区的第二内表面上。 封装接收区域被配置为接收集成电路封装，使得所接收的封装由多个安装特征支撑。 第一和第二安装特征与包装表面上的焊球阵列的第一和第二边缘中的相应空间重合。

公开(公告)号：US08461675B2

公开(公告)日：2013-06-11

申请号：US11301715

申请日：2005-12-13

申请人： Hem Takiar ,  Ken Jian Ming Wang ,  Chih-Chin Liao ,  Han-Shiao Chen

发明人： Hem Takiar ,  Ken Jian Ming Wang ,  Chih-Chin Liao ,  Han-Shiao Chen

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H05K3/242 ,  H01L21/4846 ,  H01L23/49838 ,  H01L24/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H05K3/0052 ,  H05K2201/09263 ,  H01L2924/00

摘要： A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

摘要翻译： 公开了半导体管芯衬底面板，其包括在面板上相邻的半导体封装轮廓之间的最小间隙宽度，同时确保电镀电端子的电隔离。 通过减小相邻封装轮廓之间的边界的宽度，在用于半导体封装的衬底面板上获得额外的空间。

公开(公告)号：US08193613B2

公开(公告)日：2012-06-05

申请号：US11715241

申请日：2007-03-06

申请人： Ken Jian Ming Wang ,  Ming Wang Sze

发明人： Ken Jian Ming Wang ,  Ming Wang Sze

IPC分类号： H01L23/544

CPC分类号： H01L29/0657 ,  H01L23/13 ,  H01L2924/0002 ,  Y10T428/24777 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor die having increased usable area has at least six sides. The semiconductor die has a reduced stress at each corner of the die, resulting in smaller keep out zones near the corners of the semiconductor die, which allow the placement of bond pads near each corner of the die. The semiconductor die further allows the placement of active circuitry near each corner of the semiconductor die. One embodiment results in a 5.0% increase in usable area on the semiconductor die.

摘要翻译： 根据一个实施例，具有增加的可用面积的半导体管芯具有至少六个边。 半导体管芯在管芯的每个拐角处具有减小的应力，从而在半导体管芯的拐角附近形成较小的保护区域，这允许将接合焊盘放置在管芯的每个拐角附近。 半导体管芯进一步允许在半导体管芯的每个拐角附近放置有源电路。 一个实施例导致半导体管芯上的可用面积增加了5.0％。

公开(公告)号：US08129272B2

公开(公告)日：2012-03-06

申请号：US12493582

申请日：2009-06-29

申请人： Hem Takiar ,  Cheeman Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

发明人： Hem Takiar ,  Cheeman Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

IPC分类号： H01L21/44

CPC分类号： H01L25/0657 ,  H01L21/3205 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/5386 ,  H01L24/48 ,  H01L24/64 ,  H01L24/65 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

摘要翻译： 公开了一种加强的半导体管芯基板和封装。 衬底可以包括形成有非线性边缘的接触指状物。 向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。 衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。 以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。 因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

公开(公告)号：US20090263969A1

公开(公告)日：2009-10-22

申请号：US12493582

申请日：2009-06-29

申请人： Hem Takiar ,  Cheemen Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

发明人： Hem Takiar ,  Cheemen Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

IPC分类号： H01L21/3205

CPC分类号： H01L25/0657 ,  H01L21/3205 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/5386 ,  H01L24/48 ,  H01L24/64 ,  H01L24/65 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

摘要翻译： 公开了一种加强的半导体管芯基板和封装。 衬底可以包括形成有非线性边缘的接触指状物。 向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。 衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。 以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。 因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

公开(公告)号：US20120273968A1

公开(公告)日：2012-11-01

申请号：US13544809

申请日：2012-07-09

申请人： Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Ken Jian Ming Wang ,  Cheemen Yu ,  Hem Takiar

发明人： Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Ken Jian Ming Wang ,  Cheemen Yu ,  Hem Takiar

IPC分类号： H05K1/11 ,  H01L23/48

CPC分类号： H05K1/111 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/181 ,  H05K3/4038 ,  H05K3/429 ,  H05K2201/0195 ,  H05K2201/0338 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10159 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

摘要： A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.

摘要翻译： 公开了具有共同的电连接器和接触焊盘区域的印刷电路板。 迹线和/或通孔所在接触焊盘区域可被蚀刻掉，以确保迹线，通孔和接触焊盘之间的电气隔离。

公开(公告)号：US20120187545A1

公开(公告)日：2012-07-26

申请号：US13173109

申请日：2011-06-30

申请人： Rezaur Rahman Khan ,  Edward Law ,  Ken Jian Ming Wang

发明人： Rezaur Rahman Khan ,  Edward Law ,  Ken Jian Ming Wang

IPC分类号： H01L23/488 ,  H01L21/66

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/568 ,  H01L22/20 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/1403

摘要： Methods, systems, and apparatuses are described for improved integrated circuit packages. An integrated circuit package includes a semiconductor substrate and a semiconductor die. The semiconductor substrate has opposing first and second surfaces, a plurality of vias through the semiconductor substrate, and routing one or both surfaces of the semiconductor substrate. The die is mounted to the first surface of the semiconductor substrate. An encapsulating material encapsulates the die on the first surface of the semiconductor substrate.

摘要翻译： 描述了改进的集成电路封装的方法，系统和装置。 集成电路封装包括半导体衬底和半导体管芯。 半导体衬底具有相对的第一和第二表面，穿过半导体衬底的多个通孔，并且布置半导体衬底的一个或两个表面。 芯片安装到半导体基板的第一表面。 封装材料将裸片封装在半导体衬底的第一表面上。