公开(公告)号：US08841684B2

公开(公告)日：2014-09-23

申请号：US13540583

申请日：2012-07-02

Applicant: Kazuya Ishihara ,  Jo Kinoshita

Inventor： Kazuya Ishihara ,  Jo Kinoshita

IPC: H01L33/50 ,  H01L27/15 ,  H01L33/56 ,  H01L33/58 ,  H01L25/075

CPC classification number: H01L33/56 ,  H01L25/0753 ,  H01L33/505 ,  H01L33/58 ,  H01L2224/48091 ,  H01L2924/1461 ,  H01L2924/18161 ,  H01L2933/0091 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A light-emitting device includes a circuit substrate including at least a pair of electrodes, an LED element electrically mounted on the circuit substrate, a phosphor plate disposed on an upper surface of the LED element, a diffuser plate disposed on an upper surface of the phosphor plate, and a white resin disposed on an upper surface of the circuit substrate and covering a peripheral side surface of the LED element, a peripheral side surface of the phosphor plate, and a peripheral side surface of the diffuser plate. The present invention makes it possible to obtain a planar light-emitting surface even with a plurality of LEDs, and also, a problem of color-ring occurrence caused by a phosphor may be less represented.

Abstract translation: 发光装置包括至少包括一对电极的电路基板，电气基板上电气安装的LED元件，配置在LED元件的上表面的荧光体板，设置在该LED元件的上表面的扩散板 荧光体板和布置在电路基板的上表面上的白色树脂，并且覆盖LED元件的周边侧表面，荧光体板的周边侧表面和扩散板的周边侧表面。 本发明使得即使使用多个LED也可以获得平面发光表面，并且也可能较少地表示由磷光体引起的色环发生的问题。

公开(公告)号：US08593855B2

公开(公告)日：2013-11-26

申请号：US13490713

申请日：2012-06-07

Applicant: Junya Onishi ,  Nobuyoshi Awaya ,  Mitsuru Nakura ,  Kazuya Ishihara

Inventor： Junya Onishi ,  Nobuyoshi Awaya ,  Mitsuru Nakura ,  Kazuya Ishihara

IPC: G11C11/00

CPC classification number: G06F11/1048 ,  G11C13/004 ,  G11C13/0061 ,  G11C2029/0411

Abstract: In a semiconductor memory device using a variable resistive element made of a metal oxide for storing information, a voltage amplitude of a writing voltage pulse for changing the variable resistive element to a high resistance state is set within a voltage range in which the resistance value of the high resistance state after the change increases with time. The voltage amplitude is set within the voltage range in which the resistance value of the high resistance state after the change increases toward a predetermined peak with increase in voltage amplitude. When a data error is detected by the ECC circuit, it is estimated that the data that should be in the low resistance state changes to the high resistance state, and the variable resistive elements of all memory cells from which the error is detected are written to the low resistance state to correct the error bit.

Abstract translation: 在使用由金属氧化物制成的可变电阻元件用于存储信息的半导体存储器件中，将可变电阻元件改变为高电阻状态的写入电压脉冲的电压幅度设定在电阻值 变化后的高电阻状态随时间而增加。 电压幅度设定在电压范围内，随着电压振幅的增加，变化后的高电阻状态的电阻值向预定的峰值增加。 当ECC电路检测到数据错误时，估计应该处于低电阻状态的数据变为高电阻状态，并且将检测到错误的所有存储单元的可变电阻元件写入 低电阻状态来纠正错误位。

公开(公告)号：US08422270B2

公开(公告)日：2013-04-16

申请号：US13044892

申请日：2011-03-10

Applicant: Suguru Kawabata ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

Inventor： Suguru Kawabata ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

IPC: G11C11/34

CPC classification number: G11C13/004 ,  G11C2013/0045 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

Abstract: A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.

Abstract translation: 非易失性半导体存储器件包括：位电压调整电路，对于每个位线，将选定位线和非选定位线的电位固定到预定电位以执行存储器操作，以及数据电压调整电路， 每个数据线将所选数据线和未选择的数据线的电位固定到预定电位以执行存储器操作。 每个电压调节电路包括运算放大器和晶体管，将存储器操作所需的电压输入到运算放大器的非反相输入端，运算放大器的反相输入端连接到位线 或数据线，使得位线或数据线的电位固定为运算放大器的非反相输入端的电位。

公开(公告)号：US20120075909A1

公开(公告)日：2012-03-29

申请号：US13212457

申请日：2011-08-18

Applicant: Mitsuru NAKURA ,  Kazuya Ishihara ,  Shinobu Yamazaki ,  Suguru Kawabata

Inventor： Mitsuru NAKURA ,  Kazuya Ishihara ,  Shinobu Yamazaki ,  Suguru Kawabata

IPC: G11C11/21

CPC classification number: G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/79

Abstract: Provided is a semiconductor memory device that is capable of stably programming with desirable controllability to a desired electric resistance state in a random access programming action and is provided with a variable resistance element. Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided.

Abstract translation: 提供一种半导体存储器件，其能够在随机存取编程动作中以期望的可控制性稳定地编程到期望的电阻状态，并且具有可变电阻元件。 无论作为写入动作（擦除和编程动作）的目标的存储单元的可变电阻元件的电阻状态，将可变电阻元件的电阻状态变为最低的擦除状态的擦除电压脉冲 电阻值被应用。 此后，将用于使可变电阻元件的电阻状态变为期望编程状态的编程电压脉冲被施加到编程动作目标存储单元的可变电阻元件。 通过在施加擦除电压脉冲之后始终应用编程电压脉冲，可以避免顺序施加的多个编程电压脉冲。

公开(公告)号：US20110305070A1

公开(公告)日：2011-12-15

申请号：US13157620

申请日：2011-06-10

Applicant: Kazuya ISHIHARA

Inventor： Kazuya ISHIHARA

IPC: G11C11/00

CPC classification number: G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0083 ,  G11C2013/0088 ,  G11C2213/79

Abstract: A resistance control method for a nonvolatile variable resistive element in a nonvolatile semiconductor memory device is provided. The device includes a memory cell array in which unit memory cells having nonvolatile variable resistive elements and transistors are arranged in a matrix. The memory cells that are targets of a memory operation are selected by first selection lines (word lines), second selection lines (bit lines) and third selection lines (source lines). The method includes steps of selecting one or more first selection lines, selecting a plurality of second selection lines, and applying a compensated voltage in which a change in potential of the third selection lines caused by current flowing into the third selection lines through the second selection lines is compensated in a voltage that is necessary for the memory operation, such that the voltage necessary for the memory operation is applied to all of the selected memory cells.

Abstract translation: 提供了一种用于非易失性半导体存储器件中的非易失性可变电阻元件的电阻控制方法。 该器件包括存储单元阵列，其中具有非易失性可变电阻元件和晶体管的单元存储单元排列成矩阵。 通过第一选择线（字线），第二选择线（位线）和第三选择线（源极线）来选择作为存储器操作的目标的存储器单元。 该方法包括以下步骤：选择一个或多个第一选择线，选择多个第二选择线，以及施加补偿电压，其中由通过第二选择流入第三选择线的电流引起的第三选择线的电位变化 线路以对于存储器操作所必需的电压进行补偿，使得存储器操作所需的电压被应用于所选择的所有存储单元。

公开(公告)号：US07800358B2

公开(公告)日：2010-09-21

申请号：US11478145

申请日：2006-06-30

Applicant: Yoshiyuki Akiyama ,  Kenji Nakabayashi ,  Hiroshi Onuki ,  Takatoshi Yamamoto ,  Katsuhiko Kikuchi ,  Kazuya Ishihara

Inventor： Yoshiyuki Akiyama ,  Kenji Nakabayashi ,  Hiroshi Onuki ,  Takatoshi Yamamoto ,  Katsuhiko Kikuchi ,  Kazuya Ishihara

IPC: G01B7/30

CPC classification number: G01D5/145 ,  F02D11/106 ,  F02D2200/0404 ,  G01D11/245

Abstract: After the periphery of the magnetic sensitive element is surrounded by an elastic member, the magnetic sensitive element is mold-formed with resin material. Soft epoxy or gel resin is employed as the elastic member, poured in an element-mounting space and solidified. The magnetic sensitive element is surrounded by silicone rubber. Such construction allows the magnetic sensitive element not to be affected by vibration and allows the elastic member to absorb the stress which is created due to the thermal deformation of the molded resin.

Abstract translation: 在磁敏元件周围被弹性构件包围之后，用树脂材料模塑形成磁敏元件。 使用软质环氧树脂或凝胶树脂作为弹性构件，倒入元件安装空间并固化。 磁敏元件被硅橡胶包围。 这种构造使得磁敏元件不受振动的影响，并且允许弹性构件吸收由于模制树脂的热变形而产生的应力。

公开(公告)号：US20100133083A1

公开(公告)日：2010-06-03

申请号：US12280134

申请日：2007-02-16

Applicant: Akira Watanabe ,  Kazuya Ishihara ,  Kosuke Tsuchiya

Inventor： Akira Watanabe ,  Kazuya Ishihara ,  Kosuke Tsuchiya

IPC: H01H13/76 ,  H01H9/02

CPC classification number: G02B6/006 ,  G02B6/0078 ,  H01H13/83 ,  H01H2219/044 ,  H01H2219/062

Abstract: A side surface light emitting unit illuminates, from its side surfaces, one or more objects to be illuminated which are arranged to extend in one direction on a flat surface. The side surface light emitting unit is provided with a light guide body arranged along the side surface of the objects to be illuminated, for projecting light to the side surfaces of the objects, and an LED arranged at least on one end of the light guide body. In the side surface light emitting unit, the upper surface and the lower surface, excluding the side surfaces facing the objects, are blocked from light. The objects to be illuminated, such as key switches, can be brightly illuminated by unintermittent continuous outgoing light, along the arrangement direction of the objects from one end.

Abstract translation: 侧面发光单元从其侧表面照亮被布置成在平坦表面上沿一个方向延伸的一个或多个被照明物体。 侧面发光单元设置有沿着待照明物体的侧表面布置的导光体，用于将光投射到物体的侧表面，并且LED至少布置在导光体的一端 。 在侧面发光单元中，不包括面对物体的侧面的上表面和下表面被遮挡。 被照明的物体，例如钥匙开关，可以沿着物体从一端的排列方向通过不间断的连续出射光而被明亮地照亮。

公开(公告)号：US20100118592A1

公开(公告)日：2010-05-13

申请号：US12611279

申请日：2009-11-03

Applicant: Kazuya Ishihara ,  Yutaka Ishikawa ,  Yoshiji Ohta

Inventor： Kazuya Ishihara ,  Yutaka Ishikawa ,  Yoshiji Ohta

IPC: G11C11/00 ,  G11C8/00 ,  G11C7/00

CPC classification number: G11C8/12 ,  G11C8/18 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2216/22

Abstract: Provided is a nonvolatile semiconductor memory device capable of performing a writing action for a memory cell at high speed. The device comprises: a memory cell array having a first sub-bank and a second sub-bank each having a plurality of nonvolatile memory cells arranged in a form of a matrix; a row decoder shared by the first sub-bank and the second sub-bank; a first column decoder and a second column decoder provided in the first sub-bank and the second sub-bank, respectively; and a control circuit arranged to execute alternately a first action cycle to perform a programming action in the first sub-bank and a reading action for a programming verifying action in the second sub-bank and a second action cycle to perform the reading action for the programming verifying action in the first sub-bank and the programming action in the second sub-bank.

Abstract translation: 提供了一种能够高速地对存储单元执行写入动作的非易失性半导体存储器件。 该装置包括：具有第一子库和第二子库的存储单元阵列，每个具有以矩阵形式布置的多个非易失性存储单元; 由第一子银行和第二子银行共享的行解码器; 分别设置在第一子行和第二子行中的第一列解码器和第二列解码器; 以及控制电路，被配置为交替地执行第一动作循环以在第一子存储体中执行编程动作，以及执行用于第二子存储体中的编程验证动作的读取动作和第二动作循环，以执行对于第二子存储体的读取动作 在第一子行中编程验证动作和第二子行中的编程动作。

公开(公告)号：US20090200640A1

公开(公告)日：2009-08-13

申请号：US12298818

申请日：2007-02-23

Applicant: Yasunari Hosoi ,  Kazuya Ishihara ,  Takahiro Shibuya ,  Tetsuya Ohnishi ,  Takashi Nakano

Inventor： Yasunari Hosoi ,  Kazuya Ishihara ,  Takahiro Shibuya ,  Tetsuya Ohnishi ,  Takashi Nakano

IPC: H01L29/8605 ,  H01L21/02 ,  H01L45/00

CPC classification number: H01L45/1253 ,  H01L27/101 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1273 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1633 ,  H01L45/1691

Abstract: A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged on a base substrate. The bump electrode material is contacted to a variable resistor body at a surface different from a contact surface to the lower electrode. The variable resistor body is contacted to an upper electrode at a surface different from a contact surface to the bump electrode material. Thus, a cross point region between the bump electrode material (the variable resistor body) and the upper electrode becomes an electrically contributing region of the variable resistor body, and then an area thereof can be reduced compared with that of the region regarding the conventional variable resistive element.

Abstract translation: 提供一种可变电阻元件，其包括可变电阻体的电赋能区的面积比由上电极或下电极约束的面积更小的构造及其制造方法。 凸起电极材料形成在布置在基底基板上的下电极上。 突起电极材料在与下电极的接触面不同的表面与可变电阻体接触。 可变电阻体与不同于凸块电极材料的接触表面的表面与上电极接触。 因此，凸起电极材料（可变电阻体）与上部电极之间的交叉点区域成为可变电阻体的电性区域，与现有的变量区域相比，能够减小面积 电阻元件。

公开(公告)号：US20090096568A1

公开(公告)日：2009-04-16

申请号：US12298089

申请日：2007-02-16

Applicant: Yasunari Hosoi ,  Kazuya Ishihara ,  Takahiro Shibuya ,  Tetsuya Ohnishi ,  Takashi Nakano

Inventor： Yasunari Hosoi ,  Kazuya Ishihara ,  Takahiro Shibuya ,  Tetsuya Ohnishi ,  Takashi Nakano

IPC: H01C7/10 ,  H01C13/02

CPC classification number: H01L27/101 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691 ,  Y10T29/49082

Abstract: Provided are a variable resistive element having a configuration that the area of an electrically contributing region in a variable resistor body is smaller than the area defined by an upper electrode or a lower electrode, and a method for manufacturing the variable resistive element. The cross section of a current path, in which an electric current flows through between the two electrodes via the variable resistor body at the time of applying the voltage pulse to between the two electrodes, is formed with a line width of narrower than that of any of the two electrodes and of smaller than a minimum work dimension regarding manufacturing processes, so that its area can be made smaller than that of the electrically contributing region in the variable resistive element of the prior art.

Abstract translation: 提供了一种可变电阻元件，其具有可变电阻体中的电赋值区域小于由上电极或下电极限定的面积的构造，以及制造可变电阻元件的方法。 在将电压脉冲施加到两个电极之间时，通过可变电阻体在两个电极之间流过电流的电流路径的横截面形成为比任何电极的线宽窄的线宽 并且小于关于制造工艺的最小工作尺寸，使得其面积可以比现有技术的可变电阻元件中的电赋值区的面积小。