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公开(公告)号：US20180342669A1
公开(公告)日：2018-11-29
申请号：US15856256
申请日：2017-12-28
Applicant: Dae-Shik KIM , Jeong-Heon PARK , Gwan-Hyeob KOH
Inventor： Dae-Shik KIM , Jeong-Heon PARK , Gwan-Hyeob KOH
CPC classification number: H01L43/12 , G11C11/161 , H01L27/228 , H01L29/41791 , H01L43/02 , H01L43/08
Abstract: In a method of manufacturing an MRAM device, first and second lower electrodes may be formed on first and second regions, respectively, of a substrate. First and second MTJ structures having different switching current densities from each other may be formed on the first and second lower electrodes, respectively. First and second upper electrodes may be formed on the first and second MTJ structures, respectively.
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2.发明授权公开(公告)号：US09087977B2
公开(公告)日：2015-07-21
申请号：US14254871
申请日：2014-04-16
Applicant: Jeong-Heon Park , Ki-Woong Kim , Hee-Ju Shin , Joon-Myoung Lee , Woo-Jin Kim , Jae-Hoon Kim , Se-Chung Oh , Yun-Jae Lee
Inventor： Jeong-Heon Park , Ki-Woong Kim , Hee-Ju Shin , Joon-Myoung Lee , Woo-Jin Kim , Jae-Hoon Kim , Se-Chung Oh , Yun-Jae Lee
CPC classification number: H01L43/02 , G11C11/161 , H01F10/30 , H01F10/32 , H01F10/3254 , H01F10/3272 , H01L23/528 , H01L27/222 , H01L43/08 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.
Abstract translation: 提供了具有彼此间隔开的自由层和钉扎层的半导体器件。 在自由层和钉扎层之间形成隧道势垒层。 被钉扎层可以包括下钉扎层和与下钉扎层隔开的上钉扎层。 可以在下钉扎层和上钉扎层之间形成间隔件。 非磁性接合层可以邻近间隔物设置在上或下钉扎层中的层之间。
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3.发明授权Magnetic tunneling junction devices, memories, memory systems, and electronic devices 有权磁隧道结设备，存储器，存储器系统和电子设备公开(公告)号：US08987798B2
公开(公告)日：2015-03-24
申请号：US14306792
申请日：2014-06-17
Applicant: Jeong Heon Park , Woo Chang Lim , Se Chung Oh , Young Hyun Kim , Sang Hwan Park , Jang Eun Lee
Inventor： Jeong Heon Park , Woo Chang Lim , Se Chung Oh , Young Hyun Kim , Sang Hwan Park , Jang Eun Lee
CPC classification number: H01L43/08 , G06F13/16 , G11C11/161 , G11C11/1659 , H01L43/02 , H01L43/10
Abstract: Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures.
Abstract translation: 本发明提供一种包括具有磁性层的第一结构的磁性隧道接合装置; 包括至少两个外在垂直磁化结构的第二结构，每个包括磁性层; 磁性层上的垂直磁化诱导层; 以及第一和第二结构之间的隧道屏障。
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公开(公告)号：US20130042081A1
公开(公告)日：2013-02-14
申请号：US13398640
申请日：2012-02-16
Applicant: Jeong Heon Park , Woo Chang Lim , Se Chung Oh , Young Hyun Kim , Sang Hwan Park , Jang Eun Lee
Inventor： Jeong Heon Park , Woo Chang Lim , Se Chung Oh , Young Hyun Kim , Sang Hwan Park , Jang Eun Lee
CPC classification number: H01L43/08 , G06F13/16 , G11C11/161 , G11C11/1659 , H01L43/02 , H01L43/10
Abstract: Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures.
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5.发明申请Slurry, chemical mechanical polishing method using the slurry, and method of forming metal wiring using the slurry 审中-公开使用浆料的浆料，化学机械抛光方法，以及使用该浆料形成金属配线的方法公开(公告)号：US20090068839A1
公开(公告)日：2009-03-12
申请号：US12213423
申请日：2008-06-19
Applicant: Sung-Jun Kim , Jeong-Heon Park , Chang-Ki Hong , Jae-Dong Lee
Inventor： Sung-Jun Kim , Jeong-Heon Park , Chang-Ki Hong , Jae-Dong Lee
IPC: H01L21/306
CPC classification number: C09G1/02 , H01L21/3212
Abstract: A slurry, chemical mechanical polishing (CMP) method using the slurry, and method of forming metal wiring using the slurry. The slurry may include a polishing agent, an oxidant, and at least one defect inhibitor to protect the metal film. The CMP method and method of forming metal wiring may employ one or two slurries with at least one of the slurries including at least one defect inhibitor.
Abstract translation: 使用浆料的浆料，化学机械抛光（CMP）方法以及使用该浆料形成金属配线的方法。 浆料可以包括抛光剂，氧化剂和至少一种保护金属膜的缺陷抑制剂。 形成金属布线的CMP方法和方法可以使用一种或两种浆料，其中至少一种浆料包括至少一种缺陷抑制剂。
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Patent Agency Ranking
公开(公告)号：US07294516B2
公开(公告)日：2007-11-13
申请号：US11055505
申请日：2005-02-10
Applicant: Jeong-Heon Park , Bo-Un Yoon , Jae-Dong Lee
Inventor： Jeong-Heon Park , Bo-Un Yoon , Jae-Dong Lee
Abstract: A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.
Abstract translation: 提供了一种测试图案和使用其的CMP控制方法。 测试图案设置在具有主区域和监视区域的半导体衬底的监视区域上。 测试图案包括平面区域和图案区域。 该方法包括设置测试图案的阶梯差和主图案的蚀刻厚度之间的相关性，然后将CMP施加到具有测试图案和主图案的半导体衬底预定时间。 测量测试图案的阶差，并根据相关性确定对应于测试图案的阶差的主图案的蚀刻厚度。 通过将确定的主图案的蚀刻厚度与参考值进行比较来校正抛光时间，并且将修正的抛光时间应用于随后的批次或随后的基板。
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7.发明申请Methods of fabricating thin ferroelectric layers and capacitors having ferroelectric dielectric layers therein 审中-公开制造其中具有铁电介质层的薄铁电层和电容器的方法公开(公告)号：US20060263909A1
公开(公告)日：2006-11-23
申请号：US11326485
申请日：2006-01-05
Applicant: Suk-Hun Choi , Byoung-Jae Bae , Yoon-Ho Son , Chang-Ki Hong , Jeong-Heon Park
Inventor： Suk-Hun Choi , Byoung-Jae Bae , Yoon-Ho Son , Chang-Ki Hong , Jeong-Heon Park
IPC: H01L21/00 , H01L21/8242
CPC classification number: H01L27/11507 , G11C11/22 , H01L27/11502 , H01L28/55 , H01L28/75
Abstract: Methods of forming ferroelectric layers include forming a ferroelectric layer on a substrate and chemically-mechanically polishing a surface of the ferroelectric layer by rotating a polishing pad on the surface at a rotation speed in a range from about 5 rpm to about 25 rpm. This polishing step includes pressing the polishing pad onto the surface of the ferroelectric layer at a pressure in a range from about 0.5 psi to about 3 psi. This polishing step may be followed by the step of exposing the polished surface to a rapid thermal anneal. This anneal can be performed in an inert atmosphere containing a gas selected from a group consisting of nitrogen, helium, argon and neon.
Abstract translation: 形成铁电体层的方法包括在基板上形成铁电层，并以大约5rpm至大约25rpm的旋转速度旋转表面上的抛光垫，对铁电层的表面进行化学机械抛光。 该抛光步骤包括在约0.5psi至约3psi范围内的压力下将抛光垫压在铁电层的表面上。 该抛光步骤之后可以将抛光表面暴露于快速热退火的步骤。 该退火可以在含有选自氮，氦，氩和氖的气体的惰性气氛中进行。
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公开(公告)号：US20060030155A1
公开(公告)日：2006-02-09
申请号：US11077150
申请日：2005-03-11
Applicant: Sung-Jun Kim , Jeong-Heon Park , Chang-Ki Hong , Jae-Dong Lee
Inventor： Sung-Jun Kim , Jeong-Heon Park , Chang-Ki Hong , Jae-Dong Lee
IPC: H01L21/302
CPC classification number: C09G1/02 , H01L21/3212
Abstract: A slurry, chemical mechanical polishing (CMP) method using the slurry, and method of forming metal wiring using the slurry. The slurry may include a polishing agent, an oxidant, and at least one defect inhibitor to protect the metal film. The CMP method and method of forming metal wiring may employ one or two slurries with at least one of the slurries including at least one defect inhibitor.
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9.发明申请MAGNETIC TUNNELING JUNCTION DEVICES, MEMORIES, MEMORY SYSTEMS, AND ELECTRONIC DEVICES 审中-公开磁性隧道连接装置，存储器，存储器系统和电子设备公开(公告)号：US20150155477A1
公开(公告)日：2015-06-04
申请号：US14618534
申请日：2015-02-10
Applicant: Jeong Heon PARK , Woo Chang LIM , Se Chung OH , Young Hyun KIM , Sang Hwan PARK , Jang Eun LEE
Inventor： Jeong Heon PARK , Woo Chang LIM , Se Chung OH , Young Hyun KIM , Sang Hwan PARK , Jang Eun LEE
CPC classification number: H01L43/08 , G06F13/16 , G11C11/161 , G11C11/1659 , H01L43/02 , H01L43/10
Abstract: Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures.
Abstract translation: 本发明提供一种包括具有磁性层的第一结构的磁性隧道接合装置; 包括至少两个外在垂直磁化结构的第二结构，每个包括磁性层; 磁性层上的垂直磁化诱导层; 以及第一和第二结构之间的隧道屏障。
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10.发明申请公开(公告)号：US20150048464A1
公开(公告)日：2015-02-19
申请号：US14254871
申请日：2014-04-16
Applicant: JEONG-HEON PARK , KI-WOONG KIM , HEE-JU SHIN , JOON-MYOUNG LEE , WOO-JIN KIM , JAE-HOON KIM , SE-CHUNG OH , YUN-JAE LEE
Inventor： JEONG-HEON PARK , KI-WOONG KIM , HEE-JU SHIN , JOON-MYOUNG LEE , WOO-JIN KIM , JAE-HOON KIM , SE-CHUNG OH , YUN-JAE LEE
IPC: H01L43/02
CPC classification number: H01L43/02 , G11C11/161 , H01F10/30 , H01F10/32 , H01F10/3254 , H01F10/3272 , H01L23/528 , H01L27/222 , H01L43/08 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.
Abstract translation: 提供了具有彼此间隔开的自由层和钉扎层的半导体器件。 在自由层和钉扎层之间形成隧道势垒层。 被钉扎层可以包括下钉扎层和与下钉扎层隔开的上钉扎层。 可以在下钉扎层和上钉扎层之间形成间隔件。 非磁性接合层可以邻近间隔物设置在上或下钉扎层中的层之间。
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