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    Reconfigurable logic devices
    5.
    发明授权
    Reconfigurable logic devices 有权
    可重构逻辑器件

    公开(公告)号：US08497703B2

    公开(公告)日：2013-07-30

    申请号：US13080938

    申请日：2011-04-06

    Applicant: Ho-jung Kim ,  Jai-kwang Shin ,  Hyun-sik Choi

    Inventor： Ho-jung Kim ,  Jai-kwang Shin ,  Hyun-sik Choi

    IPC: G06F7/38

    CPC classification number: H03K19/17752 ,  H03K19/17756

    Abstract: Example embodiments provide a reconfigurable logic device including at least two logic blocks having a first logic block and a second logic block, a global wire group including at least a plurality of first global wires connected to the first logic block and a plurality of second global wires connected to the second logic block, and a global controller including a plurality of first nonvolatile memory devices associated with at least one first global wire and one second global wire, the global controller configured to selectively couple the pluralities of first and second global wires based on first data stored in the associated first nonvolatile memory devices.

    Abstract translation: 示例性实施例提供了一种可重新配置逻辑设备，其包括具有第一逻辑块和第二逻辑块的至少两个逻辑块，包括连接到第一逻辑块的至少多个第一全局线的全局线组和多个第二全局线 连接到第二逻辑块，以及全局控制器，其包括与至少一个第一全局线和一个第二全局线相关联的多个第一非易失性存储器件，所述全局控制器被配置为基于多个第一和第二全局线， 存储在相关联的第一非易失性存储器件中的第一数据。

    Ferroelectric memory devices and operating methods thereof
    6.
    发明授权
    Ferroelectric memory devices and operating methods thereof 有权
    铁电存储器件及其操作方法

    公开(公告)号：US08385098B2

    公开(公告)日：2013-02-26

    申请号：US12923131

    申请日：2010-09-03

    Applicant: Ki-ha Hong ,  Jeong-seob Kim ,  Jai-kwang Shin

    Inventor： Ki-ha Hong ,  Jeong-seob Kim ,  Jai-kwang Shin

    IPC: G11C11/22

    CPC classification number: G11C11/22 ,  G11C11/223 ,  H01L21/28291 ,  H01L27/11597 ,  H01L27/1203 ,  H01L29/1606 ,  H01L29/78391

    Abstract: A ferroelectric memory device having a NAND array of a plurality of ferroelectric memory cells includes: a fully depleted channel layer; a gate electrode layer; and a ferroelectric layer located between the channel layer and the gate electrode layer. The data of the plurality of ferroelectric memory cells is erased by applying a first erase voltage to a bit line and a common source line and applying a second erase voltage to a string selection line and a ground selection line.

    Abstract translation: 具有多个铁电存储单元的NAND阵列的铁电存储器件包括：完全耗尽的沟道层; 栅电极层; 以及位于沟道层和栅电极层之间的铁电层。 通过对位线和公共源极线施加第一擦除电压并向串选择线和地选择线施加第二擦除电压来擦除多个铁电存储单元的数据。

    Spin transistor and method of operating the same
    7.
    发明授权
    Spin transistor and method of operating the same 有权
    旋转晶体管及其操作方法

    公开(公告)号：US08269293B2

    公开(公告)日：2012-09-18

    申请号：US12742221

    申请日：2008-11-04

    Applicant: Ki-Ha Hong ,  Sung-Hoon Lee ,  Jong-Seob Kim ,  Jai-Kwang Shin

    Inventor： Ki-Ha Hong ,  Sung-Hoon Lee ,  Jong-Seob Kim ,  Jai-Kwang Shin

    IPC: H01L29/82

    CPC classification number: H01L29/66984 ,  B82Y25/00 ,  H01F1/401 ,  H01F1/404 ,  H01F10/1933 ,  H01F10/1936 ,  H01F10/3254 ,  H01F10/3295 ,  H01L29/82

    Abstract: Disclosed are a spin transistor and a method of operating the spin transistor. The disclosed spin transistor includes a channel formed of a magnetic material selectively passing a spin-polarized electron having a specific direction, a source formed of a magnetic material, a drain, and a gate electrode. When a predetermined voltage is applied to the gate electrode, the channel selectively passes a spin-polarized electron having a specific direction and thus, the spin transistor is selectively turned on.

    Abstract translation: 公开了自旋晶体管和操作自旋晶体管的方法。 所公开的自旋晶体管包括由选择性地通过具有特定方向的自旋极化电子的磁性材料形成的沟道，由磁性材料形成的源极，漏极和栅电极。 当预定电压施加到栅电极时，沟道选择性地通过具有特定方向的自旋极化电子，因此自旋晶体管选择性地导通。

    Method of manufacturing high electron mobility transistor
    8.
    发明授权
    Method of manufacturing high electron mobility transistor 有权
    制造高电子迁移率晶体管的方法

    公开(公告)号：US08263449B2

    公开(公告)日：2012-09-11

    申请号：US13017361

    申请日：2011-01-31

    Applicant: Ki-ha Hong ,  U-In Chung ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang

    Inventor： Ki-ha Hong ,  U-In Chung ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang

    IPC: H01L21/338

    CPC classification number: H01L29/402 ,  H01L29/0891 ,  H01L29/66462 ,  H01L29/7786

    Abstract: A method of manufacturing a High Electron Mobility Transistor (HEMT) may include forming first and second material layers having different lattice constants on a substrate, forming a source, a drain, and a gate on the second material layer, and changing the second material layer between the gate and the drain into a different material layer, or changing a thickness of the second material layer, or forming a p-type semiconductor layer on the second material layer. The change in the second material layer may occur in an entire region of the second material layer between the gate and the drain, or only in a partial region of the second material layer adjacent to the gate. The p-type semiconductor layer may be formed on an entire top surface of the second material layer between the gate and the drain, or only on a partial region of the top surface adjacent to the gate.

    Abstract translation: 制造高电子迁移率晶体管（HEMT）的方法可以包括在衬底上形成具有不同晶格常数的第一和第二材料层，在第二材料层上形成源极，漏极和栅极，以及改变第二材料层 在栅极和漏极之间形成不同的材料层，或改变第二材料层的厚度，或在第二材料层上形成p型半导体层。 第二材料层的变化可以在栅极和漏极之间的第二材料层的整个区域中发生，或者仅在与栅极相邻的第二材料层的部分区域中发生。 p型半导体层可以形成在栅极和漏极之间的第二材料层的整个顶表面上，或者仅形成在与栅极相邻的顶表面的部分区域上。

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