公开(公告)号：US08958257B2

公开(公告)日：2015-02-17

申请号：US13808252

申请日：2011-01-07

Applicant: Jae Man Yoon

Inventor： Jae Man Yoon

IPC: G11C7/02 ,  G11C7/06 ,  G11C5/06 ,  G11C5/02 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/4074

CPC classification number: G11C7/06 ,  G11C5/025 ,  G11C5/063 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4097

Abstract: A semiconductor memory device including a memory cell array including at least one word line, at least one cell bit line, and at least one memory cell that is disposed in a region where the at least one word line and the at least one cell bit line cross each other; at least one sense amplifier that is disposed above or below the memory cell array to be overlapped with the memory cell array in a planar fashion, connected to at least one bit line connected to the at least one cell bit line, and at least one complementary bit line corresponding to the at least one bit line, and senses data stored in the at least one memory cell; a decompression unit for decompressing a signal having a lower voltage level from among a signal of the at least one bit line and a signal of the at least one complementary bit line; a boosting unit for boosting a signal having a higher voltage level from among the signal of the at least one bit line and the signal of the at least one complementary bit line; and an equalizing unit for equalizing the signal of the at least one bit line and the signal of the at least one complementary bit line.

Abstract translation: 一种半导体存储器件，包括存储单元阵列，该存储单元阵列包括至少一个字线，至少一个单元位线和至少一个存储单元，该至少一个存储单元设置在所述至少一个字线和所述至少一个单元位线 交叉对方 至少一个读出放大器，设置在存储单元阵列的上方或下方，以平面方式与存储单元阵列重叠，连接到至少一个与至少一个单元位线连接的位线;以及至少一个互补的 对应于所述至少一个位线的位线，并且感测存储在所述至少一个存储单元中的数据; 解压缩单元，用于从所述至少一个位线的信号和所述至少一个互补位线的信号中减压具有较低电压电平的信号; 升压单元，用于从所述至少一个位线的信号和所述至少一个互补位线的信号中升压具有较高电压电平的信号; 以及用于均衡所述至少一个位线的信号和所述至少一个互补位线的信号的均衡单元。

公开(公告)号：US08264022B2

公开(公告)日：2012-09-11

申请号：US12588790

申请日：2009-10-28

Applicant: Jae-man Yoon ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Makoto Yoshida ,  Bong-soo Kim

Inventor： Jae-man Yoon ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Makoto Yoshida ,  Bong-soo Kim

IPC: H01L21/70 ,  H01L21/8246 ,  H01L27/22

CPC classification number: H01L21/76834 ,  H01L21/76816 ,  H01L23/485 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/11 ,  H01L27/11517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and associated methods, the semiconductor device including a semiconductor layer including a first region and a second region, a first contact plug disposed on the semiconductor layer and electrically connected to the first region, a second contact plug disposed on the semiconductor layer and electrically connected to the second region, a conductive layer electrically connected to the first contact plug, the conductive layer having a side surface and a bottom surface, and an insulating layer disposed between the conductive layer and the second contact plug so as to insulate the conductive layer from the second contact plug, the insulating layer facing the side surface and a portion of the bottom surface of the conductive layer.

Abstract translation: 一种半导体器件及相关方法，所述半导体器件包括包括第一区域和第二区域的半导体层，设置在半导体层上并与第一区域电连接的第一接触插塞，设置在半导体层上的第二接触插塞和 电连接到第二区域，导电层电连接到第一接触插塞，导电层具有侧表面和底表面，以及绝缘层，设置在导电层和第二接触插塞之间，以使导电 层，所述绝缘层面向所述导电层的侧表面和所述底表面的一部分。

公开(公告)号：US08154065B2

公开(公告)日：2012-04-10

申请号：US12418879

申请日：2009-04-06

Applicant: Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

Inventor： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/66666

Abstract: Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.

Abstract translation: 半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。 相邻的围绕电极围绕其中的一个柱。 第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。 掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极 地区。

公开(公告)号：US20110220977A1

公开(公告)日：2011-09-15

申请号：US12760140

申请日：2010-04-14

Applicant: Jae-Man Yoon ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim ,  Yong-Chul Oh

Inventor： Jae-Man Yoon ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim ,  Yong-Chul Oh

IPC: H01L27/108 ,  H01L21/8242 ,  H01L21/336

CPC classification number: H01L27/108 ,  H01L21/84 ,  H01L27/10817 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/7833

Abstract: A semiconductor device, comprising: a vertical pillar transistor (VPT) formed on a silicon-on-insulator (SOI) substrate, the VPT including a body that has a lower portion and an upper portion, a source/drain node disposed at an upper end portion of the upper portion of the body and a drain/source node disposed at the lower portion of the body; a buried bit line (BBL) formed continuously on sidewalls and an upper surface of the lower portion, the BBL includes metal sificide; and a word line that partially enclosing the upper portion of the body of the VPT, wherein the BBL extends along a first direction and the word line extends in a second direction substantially perpendicular to the first direction. An offset region is disposed immediately beneath the word line.

Abstract translation: 一种半导体器件，包括：形成在绝缘体上硅（SOI））衬底上的垂直立柱晶体管（VPT），所述VPT包括具有下部和上部的主体，设置在上部的源极/漏极节点 本体的上部的端部和设置在主体的下部的排水/源节点; 在侧壁和下部的上表面上连续形成的埋置位线（BBL），BBL包括金属微孔; 以及字线，其部分地包围VPT的主体的上部，其中，BBL沿着第一方向延伸，并且字线在基本上垂直于第一方向的第二方向上延伸。 偏移区域设置在字线的正下方。

公开(公告)号：US07999309B2

公开(公告)日：2011-08-16

申请号：US12385433

申请日：2009-04-08

Applicant: Jae-Man Yoon ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

Inventor： Jae-Man Yoon ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/0688 ,  H01L21/8221

Abstract: In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.

Abstract translation: 在半导体器件和相关方法中，半导体器件包括衬底，衬底上的绝缘层，绝缘层上的导电结构，导电结构包括至少一种金属硅化物膜图案，导电结构上的半导体图案， 所述半导体图案从所述导电结构向上突出，栅电极至少部分地封装所述半导体图案，所述栅电极与所述导电结构间隔开，所述半导体图案的下部的第一杂质区域和所述第二杂质区域 在半导体图案的上部。

公开(公告)号：US07919378B2

公开(公告)日：2011-04-05

申请号：US12397176

申请日：2009-03-03

Applicant: Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Chul Lee

Inventor： Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Chul Lee

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.

Abstract translation: 根据本发明的一些实施例，鳍型晶体管包括与硅衬底一体形成的有源结构。 活性结构包括在源极/漏极区域下形成阻挡区的沟槽。 栅极结构形成为跨越有源结构的上表面并且覆盖有源结构的侧部的暴露的侧表面。 可以充分确保翅片型晶体管的有效沟道长度，从而可以防止晶体管的短沟道效应，并且鳍式晶体管可能具有高击穿电压。

公开(公告)号：US07902026B2

公开(公告)日：2011-03-08

申请号：US12314139

申请日：2008-12-04

Applicant: Hyun-Woo Chung ,  Jae-Man Yoon ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Gi Kim ,  Kang-Uk Kim

Inventor： Hyun-Woo Chung ,  Jae-Man Yoon ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Gi Kim ,  Kang-Uk Kim

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/76237 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of fabricating a semiconductor device having a vertical channel transistor, the method including forming a hard mask pattern on a substrate, forming a preliminary active pillar by etching the substrate using the hard mask pattern as an etch mask, reducing a width of the preliminary active pillar to form an active pillar having a width less than that of the hard mask pattern, forming a lower source/drain region by implanting impurity ions into the substrate adjacent to the active pillar using the hard mask pattern as an ion implantation mask, and forming an upper source/drain region on the active pillar and vertically separated from the lower source/drain region.

Abstract translation: 一种制造具有垂直沟道晶体管的半导体器件的方法，所述方法包括在衬底上形成硬掩模图案，通过使用硬掩模图案作为蚀刻掩模蚀刻衬底来形成预活性柱，从而减小初步 活性柱以形成宽度小于硬掩模图案的有源柱，通过使用硬掩模图案作为离子注入掩模将杂质离子注入邻近有源柱的衬底中来形成下源极/漏极区域，以及 在有源柱上形成上部源极/漏极区域，并与下部源极/漏极区域垂直分离。

公开(公告)号：US20100283094A1

公开(公告)日：2010-11-11

申请号：US12840599

申请日：2010-07-21

Applicant: Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

Inventor： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

Abstract: There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

Abstract translation: 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

公开(公告)号：US20100244124A1

公开(公告)日：2010-09-30

申请号：US12814121

申请日：2010-06-11

Applicant: Hyeoung-won Seo ,  Jae-man Yoon ,  Dong-gun Park ,  Seong-goo Kim

Inventor： Hyeoung-won Seo ,  Jae-man Yoon ,  Dong-gun Park ,  Seong-goo Kim

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L27/10876 ,  H01L29/105 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/78642

Abstract: Embodiments according to the inventive concept can provide semiconductor devices including a substrate and a plurality of active pillars arranged in a matrix on the substrate. Each of the pillars includes a channel part that includes a channel dopant region disposed in a surface of the channel part. A gate electrode surrounds an outer surface of the channel part. The plurality of active pillars may be arranged in rows in a first direction and columns in a second direction crossing the first direction.

Abstract translation: 根据本发明构思的实施例可以提供半导体器件，其包括衬底和布置在衬底上的矩阵中的多个有源柱。 每个支柱包括通道部分，其包括设置在通道部分的表面中的通道掺杂剂区域。 栅电极围绕通道部分的外表面。 多个有源支柱可以沿着第一方向排成行，并且在与第一方向交叉的第二方向上列排列。

公开(公告)号：US07776692B2

公开(公告)日：2010-08-17

申请号：US11702601

申请日：2007-02-06

Applicant: Jae-man Yoon ,  Bong-soo Kim ,  Hyeoung-won Seo ,  Kang-yoon Lee

Inventor： Jae-man Yoon ,  Bong-soo Kim ,  Hyeoung-won Seo ,  Kang-yoon Lee

IPC: H01L29/94

CPC classification number: H01L29/7828 ,  H01L27/10891 ,  H01L29/42356 ,  H01L29/66666

Abstract: A semiconductor device having a vertical channel capable of reducing the interface contact resistance between a gate electrode surrounding an active pillar and a word line connecting the gate electrode and a method of manufacturing the same is provided. The semiconductor device includes a plurality of active pillars extending in a direction perpendicular to a surface of a semiconductor substrate. A word line structure is formed on an outer periphery for connecting the active pillars disposed in the same row or column. Top and bottom source/drain regions are formed over and under the active pillars, respectively, in relation to the word line structure.

Abstract translation: 提供一种半导体器件，其具有能够降低围绕有源柱的栅极与连接栅电极的字线之间的界面接触电阻的垂直沟道及其制造方法。 半导体器件包括沿垂直于半导体衬底的表面的方向延伸的多个有源柱。 字线结构形成在用于连接设置在同一列或列中的活动柱的外周上。 顶部和底部源极/漏极区域相对于字线结构分别形成在有源支柱之上和之下。