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    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES INCLUDING GATES HAVING CONNECTION LINES THEREON
    2.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES INCLUDING GATES HAVING CONNECTION LINES THEREON 有权
    半导体集成电路设备，包括具有连接线的门

    公开(公告)号：US20150035025A1

    公开(公告)日：2015-02-05

    申请号：US14516201

    申请日：2014-10-16

    Applicant: Bong-Soo KIM ,  Soo-Ho SHIN ,  Ho-In RYU ,  Hyeong-Sun HONG

    Inventor： Bong-Soo KIM ,  Soo-Ho SHIN ,  Ho-In RYU ,  Hyeong-Sun HONG

    IPC: H01L29/78 ,  H01L27/108

    CPC classification number: H01L29/78 ,  H01L27/0207 ,  H01L27/10805 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/7833

    Abstract: Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.

    Abstract translation: 提供了包括其间具有台阶差的栅极图案和插入在栅极图案之间的连接线的半导体集成电路（IC）装置。 半导体IC器件包括包括外围有源区，单元有源区和器件隔离层的半导体衬底。 单元栅极图案设置在单元有源区和器件隔离层上。 外围栅极图案设置在外围有源区域上。 电池电节点设置在与电池栅极图案相邻的电池有源区域上。 外围电节点设置在与外围栅极图案相邻的外围有源区域上。 连接线设置在设置在器件隔离层上的单元栅极图案上。 连接线连接在单元栅极图案和外围栅极图案之间。

    Time synchronization and routing method in wireless sensor network, and apparatus for enabling the method
    3.
    发明授权
    Time synchronization and routing method in wireless sensor network, and apparatus for enabling the method 有权
    无线传感器网络中的时间同步和路由方法，以及启用该方法的装置

    公开(公告)号：US08848584B2

    公开(公告)日：2014-09-30

    申请号：US12667298

    申请日：2008-07-11

    Applicant: Chang Sub Shin ,  Gwang Ja Jin ,  So Young Hwang ,  Yoonmee Doh ,  Bong Soo Kim ,  Cheol Sig Pyo ,  Jong-Suk Chae

    Inventor： Chang Sub Shin ,  Gwang Ja Jin ,  So Young Hwang ,  Yoonmee Doh ,  Bong Soo Kim ,  Cheol Sig Pyo ,  Jong-Suk Chae

    IPC: G08C17/00 ,  H04J3/06 ,  H04W56/00

    CPC classification number: H04J3/0679 ,  H04J3/0667 ,  H04W56/002 ,  Y02D70/144 ,  Y02D70/166 ,  Y02D70/22

    Abstract: A time synchronization method in a wireless sensor network, a low power routing method using a reservation scheme, and an apparatus for performing the method are provided. The time synchronization method in the wireless sensor network may include: receiving a first synchronization request command packet from a parent node that manages time synchronization for a predetermined synchronization region; receiving, from the parent node, a second synchronization request command packet that has a transmission timestamp value of the first synchronization request command packet; and performing time synchronization for a child node based on a reception time of the first synchronization request command packet, a reception time of the second synchronization request command packet, and the transmission timestamp value of the first synchronization request command packet.

    Abstract translation: 提供无线传感器网络中的时间同步方法，使用预约方案的低功率路由方法以及用于执行该方法的装置。 无线传感器网络中的时间同步方法可以包括：从管理预定同步区域的时间同步的父节点接收第一同步请求命令分组; 从所述父节点接收具有所述第一同步请求命令分组的传输时间戳值的第二同步请求命令分组; 以及基于所述第一同步请求命令分组的接收时间，所述第二同步请求命令分组的接收时间和所述第一同步请求命令分组的传输时间戳值来执行子节点的时间同步。

    Integrated circuit devices having buried interconnect structures therein that increase interconnect density
    4.
    发明授权
    Integrated circuit devices having buried interconnect structures therein that increase interconnect density 有权
    其中具有掩埋互连结构的集成电路器件增加互连密度

    公开(公告)号：US08729658B2

    公开(公告)日：2014-05-20

    申请号：US13789028

    申请日：2013-03-07

    Applicant: Bong-Soo Kim ,  Kwang-Youl Chun ,  Sang-Bin Ahn

    Inventor： Bong-Soo Kim ,  Kwang-Youl Chun ,  Sang-Bin Ahn

    IPC: H01L29/00

    CPC classification number: H01L23/481 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/485 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer. A second electrical interconnect is also provided, which extends on: (i) an upper surface of the first trench isolation region, (ii) the electrically insulating capping pattern; and (iii) the sidewall of the recess. The first and second electrical interconnects extend across the semiconductor substrate in first and second orthogonal directions, respectively.

    Abstract translation: 集成电路器件包括在其中具有多个沟槽隔离区域的半导体衬底，其中限定了它们之间的相应的半导体有源区。 沟槽设置在半导体衬底中。 沟槽具有分别限定与第一沟槽隔离区域和第一有源区域相对的界面的第一和第二相对的侧壁。 第一电互连设置在沟槽的底部。 提供了一种电绝缘覆盖图案，其在第一电互连和沟槽的顶部之间延伸。 还提供了互连绝缘层，其将沟槽的第一和第二侧壁和底部排列。 互连绝缘层在第一电互连和第一有源区之间延伸。 在第一活动区域设置有凹部。 凹部具有限定与互连绝缘层的界面的侧壁。 还提供了第二电互连，其延伸在：（i）第一沟槽隔离区的上表面，（ii）电绝缘封盖图案; 和（iii）凹槽的侧壁。 第一和第二电互连分别在第一和第二正交方向跨越半导体衬底延伸。

    Mobile terminal for displaying an image on an external screen and controlling method thereof
    6.
    发明授权
    Mobile terminal for displaying an image on an external screen and controlling method thereof 有权
    用于在外部屏幕上显示图像的移动终端及其控制方法

    公开(公告)号：US08351983B2

    公开(公告)日：2013-01-08

    申请号：US12421606

    申请日：2009-04-09

    Applicant: Jong Hwan Kim ,  Bong Soo Kim

    Inventor： Jong Hwan Kim ,  Bong Soo Kim

    IPC: H04M1/00

    CPC classification number: H04N9/3173

    Abstract: A mobile terminal includes a projector module projecting an image onto an external surface; a display having a touchscreen; and a controller configured to receive a control signal corresponding to a touch input received via the display, wherein the control signal is for adjusting at least a size or a position of an external display area formed on the external surface such that the external display area is adjusted based on a touch pattern of the touch input, to adjust the external display area in response to the control signal, and to control the projector module to project the image on the adjusted external display area, wherein a screen area set and positioned according to the touch input is displayed via the touchscreen and the external display area is adjusted according to a size and a position of the screen area.

    Abstract translation: 移动终端包括将图像投影到外表面上的投影仪模块; 具有触摸屏的显示器; 以及控制器，被配置为接收与经由所述显示器接收的触摸输入相对应的控制信号，其中所述控制信号用于至少调整形成在所述外表面上的外部显示区域的尺寸或位置，使得所述外部显示区域 基于触摸输入的触摸图案进行调整，响应于控制信号调整外部显示区域，并且控制投影仪模块将图像投影到调整后的外部显示区域上，其中根据 通过触摸屏显示触摸输入，并且根据屏幕区域的大小和位置来调整外部显示区域。

    Methods of Fabricating Semiconductor Devices Having Buried Word Line Interconnects
    7.
    发明申请
    Methods of Fabricating Semiconductor Devices Having Buried Word Line Interconnects 有权
    制造埋入字线互连的半导体器件的方法

    公开(公告)号：US20120264280A1

    公开(公告)日：2012-10-18

    申请号：US13473751

    申请日：2012-05-17

    Applicant: Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

    Inventor： Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

    IPC: H01L21/768

    CPC classification number: H01L27/10891 ,  H01L21/743 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

    Abstract: A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.

    Abstract translation: 半导体器件包括具有限定在其中的单元区域和外围电路区域的半导体衬底。 掩埋字线设置在单元区域中的基板中，并且具有比单元区域中的单元有源区域的顶表面低的顶表面。 栅极线设置在外围电路区域中的衬底上。 字线互连设置在外围电路区域中的衬底中，字线互连包括接触掩埋字线的第一部分，并且具有低于电池有源区的顶表面的顶表面和重叠的第二部分 通过并与栅极线接触。

    Method of fabricating semiconductor device with cell epitaxial layers partially overlap buried cell gate electrode
    9.
    发明授权
    Method of fabricating semiconductor device with cell epitaxial layers partially overlap buried cell gate electrode 有权
    制造具有电池外延层的半导体器件的方法部分地覆盖埋电池栅电极

    公开(公告)号：US08053307B2

    公开(公告)日：2011-11-08

    申请号：US12662393

    申请日：2010-04-14

    Applicant: Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

    Inventor： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

    IPC: H01L21/8234

    CPC classification number: H01L29/66628 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

    Abstract: A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

    Abstract translation: 半导体器件可以包括具有电池有源区的衬底。 可以在电池活性区域中形成电池栅电极。 单元栅极覆盖层可以形成在单元栅电极上。 至少两个电池外延层可以形成在电池有源区上。 至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。 电池杂质区域可以设置在电池活性区域中。 电池杂质区域可以对应于至少两个电池外延层中的相应一个。

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