公开(公告)号：US08243528B2

公开(公告)日：2012-08-14

申请号：US12491668

申请日：2009-06-25

申请人： Il Young Kwon

发明人： Il Young Kwon

IPC分类号： G11C11/34

CPC分类号： G11C16/16

摘要： In an erase method of a flash device, including a page buffer configured to transfer a virtual voltage in response to a discharge signal and further comprising strings each including memory cells and coupled to the page buffer via a respective bit line, applying a ground voltage to a gate of each of the memory cells and erasing the memory cells coupled to a selected bit line by supplying the virtual voltage wherein the virtual voltage is applied to the selected bit line and a unselected bit line.

摘要翻译： 在闪存器件的擦除方法中，包括被配置为响应于放电信号传送虚拟电压的页缓冲器，并且还包括每个包括存储器单元并且经由相应位线耦合到页缓冲器的串，将接地电压施加到 每个存储器单元的栅极，并且通过提供其中虚拟电压被施加到所选择的位线和未选择的位线的虚拟电压来擦除耦合到所选位线的存储器单元。

公开(公告)号：US07018930B2

公开(公告)日：2006-03-28

申请号：US10292540

申请日：2002-11-12

申请人： Sung-Kwon Lee ,  Sang-Ik Kim ,  Il-Young Kwon ,  Kuk-Han Yoon ,  Phil-Goo Kong ,  Jin-Sung Oh ,  Jin-Ki Jung ,  Jae-Young Kim ,  Kwang-Ok Kim ,  Myung-Kyu Ahn

发明人： Sung-Kwon Lee ,  Sang-Ik Kim ,  Il-Young Kwon ,  Kuk-Han Yoon ,  Phil-Goo Kong ,  Jin-Sung Oh ,  Jin-Ki Jung ,  Jae-Young Kim ,  Kwang-Ok Kim ,  Myung-Kyu Ahn

IPC分类号： H01L21/302

CPC分类号： H01L21/31144 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for fabricating a semiconductor device capable of minimizing deformations of a photoresist pattern and losses of a hard mask. The method includes the steps of: forming an insulating layer for a hard mask on an etch-target layer; forming a sacrificial layer on the insulating layer; forming a photoresist pattern on the sacrificial layer; forming at least one sacrificial hard mask by etching the sacrificial layer with the photoresist pattern as an etching mask; forming the hard mask by etching the insulating layer with the sacrificial hard mask as an etching mask; and forming a predetermined number of patterns by etching the etch-target layer with use of the sacrificial hard mask and the hard mask as etching masks.

公开(公告)号：US07339211B2

公开(公告)日：2008-03-04

申请号：US10625277

申请日：2003-07-23

申请人： Dong-Sauk Kim ,  Ho-Seok Lee ,  Byung-Jun Park ,  Il-Young Kwon ,  Jong-Min Lee ,  Hyeong-Soo Kim ,  Jin-Woong Kim ,  Hyung-Bok Choi ,  Dong-Woo Shin

发明人： Dong-Sauk Kim ,  Ho-Seok Lee ,  Byung-Jun Park ,  Il-Young Kwon ,  Jong-Min Lee ,  Hyeong-Soo Kim ,  Jin-Woong Kim ,  Hyung-Bok Choi ,  Dong-Woo Shin

IPC分类号： H01L27/148 ,  H01L29/768

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10814

摘要： Semiconductor devices and methods of manufacture thereof are disclosed that are capable of preventing a short of lower electrodes caused by a leaning or lifting phenomenon while forming the lower electrodes and securing enough capacitance of a capacitor by widening an effective capacitor area. The inventive semiconductor device includes: a plurality of capacitor plugs disposed in an orderly separation distance; and a plurality of lower electrodes used for a capacitor and disposed in an orderly separation distance to be respectively connected with the capacitor plugs.

摘要翻译： 公开了半导体装置及其制造方法，其能够通过扩大有效的电容器面积来形成下部电极并且通过扩大电容器的足够的电容来防止由倾斜或提升现象引起的较短的下部电极。 本发明的半导体器件包括：以有序的间隔距离设置的多个电容器插头; 以及多个用于电容器的下电极，并且以与电容器插头分别连接的有序分隔距离设置。

公开(公告)号：US20100027353A1

公开(公告)日：2010-02-04

申请号：US12491668

申请日：2009-06-25

申请人： Il Young Kwon

发明人： Il Young Kwon

IPC分类号： G11C16/16 ,  G11C7/10

CPC分类号： G11C16/16

摘要： In an erase method of a flash device, including a page buffer configured to transfer a virtual voltage in response to a discharge signal and further comprising strings each including memory cells and coupled to the page buffer via a respective bit line, applying a ground voltage to a gate of each of the memory cells and erasing the memory cells coupled to a selected bit line by supplying the virtual voltage wherein the virtual voltage is applied to the selected bit line and a unselected bit line.

摘要翻译： 在闪存器件的擦除方法中，包括被配置为响应于放电信号传送虚拟电压的页缓冲器，并且还包括每个包括存储器单元并且经由相应位线耦合到页缓冲器的串，将接地电压施加到 每个存储器单元的栅极，并且通过提供其中虚拟电压被施加到所选择的位线和未选择的位线的虚拟电压来擦除耦合到所选位线的存储器单元。

公开(公告)号：US07572729B2

公开(公告)日：2009-08-11

申请号：US11635909

申请日：2006-12-08

申请人： Il Young Kwon

发明人： Il Young Kwon

IPC分类号： H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76883 ,  H01L27/11517

摘要： A method of manufacturing semiconductor devices, including the steps of forming an insulating layer on a semiconductor substrate in which predetermined structures are formed, and etching the insulating layer to expose a predetermined region of the semiconductor substrate, thereby forming a contact hole, forming an insulating layer on the sides of the contact hole, and forming a conductive layer within the contact hole, forming a contact plug. It is possible to prevent a short problem by sufficiently securing a distance between a drain contact plug and a virtual power line.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在形成有预定结构的半导体衬底上形成绝缘层，并蚀刻绝缘层以暴露半导体衬底的预定区域，从而形成接触孔，形成绝缘层 在接触孔的侧面上形成导电层，形成接触插塞。 可以通过充分确保漏极接触插头和虚拟电源线之间的距离来防止短的问题。

公开(公告)号：US20130240994A1

公开(公告)日：2013-09-19

申请号：US13598604

申请日：2012-08-29

申请人： Ki Hong LEE ,  Seung Ho Pyi ,  Il Young Kwon

发明人： Ki Hong LEE ,  Seung Ho Pyi ,  Il Young Kwon

IPC分类号： H01L29/423 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76877 ,  H01L29/4238 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes a substrate, and a gate line, located over the substrate, which includes a first conductive layer and one or more second conductive pattern layers located in the first conductive layer. The second conductive pattern layer comprises a metal layer to thus reduce resistance of a gate line.

公开(公告)号：US08890251B2

公开(公告)日：2014-11-18

申请号：US13598604

申请日：2012-08-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Il Young Kwon

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Il Young Kwon

IPC分类号： H01L29/40

CPC分类号： H01L27/11582 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76877 ,  H01L29/4238 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes a substrate, and a gate line, located over the substrate, which includes a first conductive layer and one or more second conductive pattern layers located in the first conductive layer. The second conductive pattern layer comprises a metal layer to thus reduce resistance of a gate line.

摘要翻译： 半导体器件包括位于衬底上方的衬底和栅极线，栅极线包括第一导电层和位于第一导电层中的一个或多个第二导电图案层。 第二导电图案层包括金属层，从而降低栅极线的电阻。

公开(公告)号：US08709894B2

公开(公告)日：2014-04-29

申请号：US13234422

申请日：2011-09-16

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Il Young Kwon ,  Jin Ho Bin

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Il Young Kwon ,  Jin Ho Bin

IPC分类号： H01L21/336

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/324 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/66833 ,  H01L29/7926

摘要： A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.

摘要翻译： 公开了一种3D结构的非易失性半导体存储器件及其制造方法。 一个这样的器件包括在源极/漏极区域的n +区域; 源/漏区的p +区; 以及在n +区域和p +区域之间的扩散阻挡材料。 n +区域基本上与p +区隔离。

公开(公告)号：US20070238286A1

公开(公告)日：2007-10-11

申请号：US11635909

申请日：2006-12-08

申请人： Il Young Kwon

发明人： Il Young Kwon

IPC分类号： H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76883 ,  H01L27/11517

摘要： A method of manufacturing semiconductor devices, including the steps of forming an insulating layer on a semiconductor substrate in which predetermined structures are formed, and etching the insulating layer to expose a predetermined region of the semiconductor substrate, thereby forming a contact hole, forming an insulating layer on the sides of the contact hole, and forming a conductive layer within the contact hole, forming a contact plug. It is possible to prevent a short problem by sufficiently securing a distance between a drain contact plug and a virtual power line.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在形成有预定结构的半导体衬底上形成绝缘层，并蚀刻绝缘层以暴露半导体衬底的预定区域，从而形成接触孔，形成绝缘层 在接触孔的侧面上形成导电层，形成接触插塞。 可以通过充分确保漏极接触插头和虚拟电源线之间的距离来防止短的问题。

公开(公告)号：US20070085128A1

公开(公告)日：2007-04-19

申请号：US11608672

申请日：2006-12-08

申请人： Dong-Sauk KIM ,  Ho-Seok Lee ,  Byung-Jun Park ,  Il-Young Kwon ,  Jong-Min Lee ,  Hyeong-Soo Kim ,  Jin-Woong Kim ,  Hyung-Bok Choi ,  Dong-Woo Shin

发明人： Dong-Sauk KIM ,  Ho-Seok Lee ,  Byung-Jun Park ,  Il-Young Kwon ,  Jong-Min Lee ,  Hyeong-Soo Kim ,  Jin-Woong Kim ,  Hyung-Bok Choi ,  Dong-Woo Shin

IPC分类号： H01L29/76

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10814

摘要： Semiconductor devices and methods of manufacture thereof are disclosed that are capable of preventing a short of lower electrodes caused by a leaning or lifting phenomenon while forming the lower electrodes and securing enough capacitance of a capacitor by widening an effective capacitor area. The inventive semiconductor device includes: a plurality of capacitor plugs disposed in an orderly separation distance; and a plurality of lower electrodes used for a capacitor and disposed in an orderly separation distance to be respectively connected with the capacitor plugs.

摘要翻译： 公开了半导体装置及其制造方法，其能够通过扩大有效的电容器面积来形成下部电极并且通过扩大电容器的足够的电容来防止由倾斜或提升现象引起的较短的下部电极。 本发明的半导体器件包括：以有序的间隔距离设置的多个电容器插头; 以及多个用于电容器的下电极，并且以与电容器插头分别连接的有序分隔距离设置。