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    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
    半导体器件及其形成方法

    公开(公告)号：US20110133283A1

    公开(公告)日：2011-06-09

    申请号：US12649637

    申请日：2009-12-30

    申请人： Jeong Hoon PARK ,  Dong Sauk KIM

    发明人： Jeong Hoon PARK ,  Dong Sauk KIM

    IPC分类号： H01L27/06 ,  H01L21/8234

    CPC分类号： H01L21/823456 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236

    摘要： A semiconductor device includes a structure in which a difference in height between a cell region and a peripheral region are formed so that a buried gate structure of the cell region is substantially equal in height to the gate of the peripheral region, whereby a bit line and a storage node contact can be more easily formed in the cell region and parasitic capacitance can be decreased decreased. The semiconductor device includes a cell region including a gate buried in a substrate, and a peripheral region adjacent to the cell region, where a step height between a surface of the cell and a surface of the peripheral region is generated.

    摘要翻译： 半导体器件包括其中形成单元区域和外围区域之间的高度差的结构，使得单元区域的掩埋栅极结构的高度与周边区域的栅极高度相等，由此位线 可以更容易地在单元区域中形成存储节点接触，并且可以减小寄生电容。 半导体器件包括包含埋在衬底中的栅极的单元区域和与单元区域相邻的周边区域，其中生成单元表面和外围区域表面之间的台阶高度。

    Method for forming contact hole in semiconductor device
    4.
    发明申请
    Method for forming contact hole in semiconductor device 有权
    在半导体器件中形成接触孔的方法

    公开(公告)号：US20070148964A1

    公开(公告)日：2007-06-28

    申请号：US11448714

    申请日：2006-06-08

    申请人： Dong-Yeol Lee ,  Dong-Goo Choi ,  Dong-Sauk Kim

    发明人： Dong-Yeol Lee ,  Dong-Goo Choi ,  Dong-Sauk Kim

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76802 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76829

    摘要： A method for forming a contact hole in a semiconductor device includes forming gate lines on a substrate, forming a bit line pattern by forming a bit line and a bit line hard mask in sequential order over the substrate, forming an inter-layer insulation layer having a multiple-layer structure including an etch stop layer over the substrate, forming a contact mask over the inter-layer insulation layer, performing a first etching process to etch a first portion of the inter-layer insulation layer above the etch stop layer, using the contact mask as an etch mask, and performing a second etching process to etch the etch stop layer, a second portion of the inter-layer insulation layer below the etch stop layer, and the bit line hard mask to form a contact hole exposing a portion of the bit line.

    摘要翻译： 一种用于在半导体器件中形成接触孔的方法包括在衬底上形成栅极线，通过在衬底上依次形成位线和位线硬掩模形成位线图案，形成层间绝缘层，该层间绝缘层具有 包括在衬底上的蚀刻停止层的多层结构，在层间绝缘层上形成接触掩模，执行第一蚀刻工艺以蚀刻蚀刻停止层上方的层间绝缘层的第一部分，使用 所述接触掩模作为蚀刻掩模，以及执行蚀刻所述蚀刻停止层的第二蚀刻工艺，所述蚀刻停止层下面的所述层间绝缘层的第二部分和所述位线硬掩模以形成暴露于 位线的一部分。

    Method for fabricating semiconductor device
    6.
    发明授权
    Method for fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07226829B2

    公开(公告)日：2007-06-05

    申请号：US10749533

    申请日：2003-12-30

    申请人： Chang-Youn Hwang ,  Dong-Sauk Kim ,  Jin-Ki Jung

    发明人： Chang-Youn Hwang ,  Dong-Sauk Kim ,  Jin-Ki Jung

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention is related to a method for forming a storage node of a semiconductor device. The method includes the steps of: (a) forming a plurality of bit line patterns, each including a wire and a hard mask sequentially stacked on a surface of a substrate structure; (b) sequentially forming a first barrier layer and a first inter-layer insulation layer along a profile containing bit line patterns until filling spaces between the bit line patterns; (c) etching the first inter-layer insulation layer until a partial portion of the first inter-layer insulation layer remains on each space between the bit line patterns; (d) forming a second barrier layer on the first inter-layer insulation layer and the first barrier layer; and (e) etching the first and the second barrier layers and the remaining first inter-layer insulation layer to expose a surface of the substrate structure disposed between the bit line patterns.

    摘要翻译： 本发明涉及一种用于形成半导体器件的存储节点的方法。 该方法包括以下步骤：（a）形成多个位线图案，每个位线图案包括依次层叠在基板结构的表面上的导线和硬掩模; （b）沿着包含位线图形的轮廓依次形成第一阻挡层和第一层间绝缘层，直到填充位线图形之间的空间; （c）蚀刻第一层间绝缘层，直到第一层间绝缘层的部分部分保留在位线图案之间的每个空间上; （d）在第一层间绝缘层和第一阻挡层上形成第二阻挡层; 和（e）蚀刻第一和第二阻挡层和剩余的第一层间绝缘层以暴露位于位线图案之间的衬底结构的表面。

    Method of forming a tungsten plug in a semiconductor device
    8.
    发明授权
    Method of forming a tungsten plug in a semiconductor device 失效
    在半导体器件中形成钨插塞的方法

    公开(公告)号：US5668064A

    公开(公告)日：1997-09-16

    申请号：US606305

    申请日：1996-02-23

    申请人： Sang Hoon Park ,  Dong Sauk Kim ,  Ju Il Lee

    发明人： Sang Hoon Park ,  Dong Sauk Kim ,  Ju Il Lee

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/60

    CPC分类号： H01L21/76838 ,  H01L23/5226 ,  H01L2924/0002

    摘要： The present invention discloses a method of forming a tungsten plug within a via hole in which it sequentially forms a barrier metal layer and a tungsten layer on a insulating film including the via hole, forms a photoresist pattern of which size is enough to cover the via hole on the tungsten layer in the upper side of the via hole, etching the tungsten layer by sequentially performing an isotropic etching process and an anisotropic etching process using the photoresist pattern as an etching mask and, after the photoresist pattern is removed, etching the projections of the tungsten layer by performing the anisotropic etching process.

    摘要翻译： 本发明公开了一种在通孔内形成钨插塞的方法，其中它依次在包括通孔的绝缘膜上形成阻挡金属层和钨层，形成尺寸足以覆盖通孔的光致抗蚀剂图案 在通孔的上侧的钨层上的孔，通过依次进行各向同性蚀刻工艺和使用光致抗蚀剂图案作为蚀刻掩模的各向异性蚀刻工艺蚀刻钨层，并且在除去光致抗蚀剂图案之后，蚀刻突起 通过进行各向异性蚀刻处理。

    Method for forming contact hole in semiconductor device
    9.
    发明授权
    Method for forming contact hole in semiconductor device 有权
    在半导体器件中形成接触孔的方法

    公开(公告)号：US07521347B2

    公开(公告)日：2009-04-21

    申请号：US11448714

    申请日：2006-06-08

    申请人： Dong-Yeol Lee ,  Dong-Goo Choi ,  Dong-Sauk Kim

    发明人： Dong-Yeol Lee ,  Dong-Goo Choi ,  Dong-Sauk Kim

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76802 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76829

    摘要： A method for forming a contact hole in a semiconductor device includes forming gate lines on a substrate, forming a bit line pattern by forming a bit line and a bit line hard mask in sequential order over the substrate, forming an inter-layer insulation layer having a multiple-layer structure including an etch stop layer over the substrate, forming a contact mask over the inter-layer insulation layer, performing a first etching process to etch a first portion of the inter-layer insulation layer above the etch stop layer, using the contact mask as an etch mask, and performing a second etching process to etch the etch stop layer, a second portion of the inter-layer insulation layer below the etch stop layer, and the bit line hard mask to form a contact hole exposing a portion of the bit line.

    摘要翻译： 一种用于在半导体器件中形成接触孔的方法包括在衬底上形成栅极线，通过在衬底上依次形成位线和位线硬掩模形成位线图案，形成层间绝缘层，该层间绝缘层具有 包括在衬底上的蚀刻停止层的多层结构，在层间绝缘层上形成接触掩模，执行第一蚀刻工艺以蚀刻蚀刻停止层上方的层间绝缘层的第一部分，使用 所述接触掩模作为蚀刻掩模，以及执行蚀刻所述蚀刻停止层的第二蚀刻工艺，所述蚀刻停止层下面的所述层间绝缘层的第二部分和所述位线硬掩模以形成暴露于 位线的一部分。