公开(公告)号：US08598719B2

公开(公告)日：2013-12-03

申请号：US12997376

申请日：2009-06-03

申请人： Mitsuo Sugino ,  Hideki Hara ,  Toru Meura

发明人： Mitsuo Sugino ,  Hideki Hara ,  Toru Meura

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5389 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/562 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29366 ,  H01L2224/29386 ,  H01L2224/8385 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/1301 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K3/284 ,  H05K3/305 ,  H05K2201/068 ,  H05K2201/10674 ,  H05K2203/1322 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/05341 ,  H01L2924/05442 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

摘要： A semiconductor element mounting board includes: a board having surfaces; a semiconductor element provided at a side of one of the surfaces of the board; a bonding agent layer through which the board and the semiconductor element are bonded together, the bonding agent layer having a storage modulus at 25° C. of 5 to 1,000 MPa; a first layer into which the semiconductor element is embedded, the first layer provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer. In the semiconductor element mounting board, a coefficient of thermal expansion of each surface layer in an inplane direction thereof measured based on JIS C 6481 at a temperature of 20° C. to a glass-transition temperature Tga° C., which is measured based on JIS C 6481, is 40 ppm/° C. or lower.

摘要翻译： 半导体元件安装板包括：具有表面的板; 设置在所述板的一个表面的一侧的半导体元件; 将基板和半导体元件结合在一起的接合剂层，25℃下的储能模量为5〜1000MPa的接合剂层; 第一层，半导体元件被嵌入其中，第一层设置在板的一个表面上; 设置在所述板的另一个表面上的第二层，所述第二层由与所述第一层相同的材料构成，所述第二层的构成材料具有与所述第一层的构成材料相同的组成比 ; 以及分别设置在第一和第二层上的表面层，每个表面层由至少单层形成。 在半导体元件安装基板中，基于JIS C 6481在20℃的温度下测定各面层的面内方向的热膨胀系数至玻璃化转变温度Tga°C 在JIS C 6481中为40ppm /℃以下。

公开(公告)号：US08494019B2

公开(公告)日：2013-07-23

申请号：US12750838

申请日：2010-03-31

申请人： Yoshihiko Iga ,  Hiroshi Moriya ,  Yutaka Inoue ,  Hideki Hara ,  Keiichi Miyauchi

发明人： Yoshihiko Iga ,  Hiroshi Moriya ,  Yutaka Inoue ,  Hideki Hara ,  Keiichi Miyauchi

IPC分类号： H01S5/00

CPC分类号： H01S5/4031 ,  H01S5/0224 ,  H01S5/02272 ,  H01S5/024 ,  H01S5/02476 ,  H01S5/0425

摘要： Within a semiconductor laser device, mounting a semiconductor laser element array of multi-beam structure on a sub-mount, the semiconductor laser element array of multi-beam structure comprises one piece of a semiconductor substrate 11; a common electrode 1, which is formed on a first surface of the semiconductor substrate; a semiconductor layer 2, which is formed on the other surface of the semiconductor substrate, and has a plural number of light emitting portions 7 within an inside thereof; a plural number of anode electrodes 3 of a second conductivity type, which are formed above the plural number of light emitting portions, respectively; and a supporting portion 25, which is provided outside a region of forming the light emitting portions, wherein on one surface of the sub-mount is connected an electrode 3 of the semiconductor laser element array through a solder 4, and that solder 4 is formed to cover a supporting portion and an electrode neighboring thereto, and further on the electrode 3 is formed a groove portion 9 between the supporting portion 25 neighboring and the light emitting portions 7.

摘要翻译： 在半导体激光器件中，将多光束结构的半导体激光元件阵列安装在子座上，多光束结构的半导体激光元件阵列包括一片半导体衬底11; 公共电极1，形成在半导体衬底的第一表面上; 半导体层2，其形成在半导体衬底的另一个表面上，并且在其内部具有多个发光部分7; 分别形成在多个发光部分上方的多个第二导电类型的阳极电极3; 以及支撑部25，其设置在形成发光部的区域的外侧，其中，在所述副安装座的一个表面上，通过焊料4与所述半导体激光元件阵列的电极3连接，形成所述焊料4 覆盖支撑部分和与其相邻的电极，并且在电极3上还形成有在相邻的支撑部分25和发光部分7之间的槽部分9。

公开(公告)号：US20110308848A1

公开(公告)日：2011-12-22

申请号：US13148774

申请日：2010-02-08

申请人： Yuka Ito ,  Kenichi Kaneda ,  Yasuaki Mitsui ,  Iji Onozuka ,  Noriyuki Ohigashi ,  Hideki Hara

发明人： Yuka Ito ,  Kenichi Kaneda ,  Yasuaki Mitsui ,  Iji Onozuka ,  Noriyuki Ohigashi ,  Hideki Hara

IPC分类号： H05K1/18 ,  H05K3/00 ,  B32B3/00

CPC分类号： H05K3/045 ,  H05K3/107 ,  H05K3/281 ,  H05K3/421 ,  H05K3/465 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09563 ,  Y10T29/49124 ,  Y10T428/24355

摘要： Disclosed are a composite body, a method for producing the composite body and a semiconductor device, the composite body comprising a resin layer and a fine wiring and/or via hole being formed in the resin layer, having high adhesion and high reliability, and being capable of high frequencies. Also disclosed are a resin composition and a resin sheet, both of which can provide such a composite body.The composite body comprises a resin layer and an electroconductive layer, wherein a groove having a maximum width of 1 μm or more and 10 μm or less is on a surface of the resin layer; the electroconductive layer is inside the groove; and a surface of the resin layer being in contact with the electroconductive layer has an arithmetic average roughness (Ra) of 0.05 μm or more and 0.45 μm or less, and/or wherein the resin layer has a via hole having a diameter of 1 μm or more and 25 μm or less; the electroconductive layer is inside the via hole; and a surface of the resin layer of the inside of the via hole has an arithmetic average roughness (Ra) of 0.05 μm or more and 0.45 μm or less. The resin composition comprises an inorganic filler and a thermosetting resin, wherein the inorganic filler contains coarse particles having a diameter of more than 2 μm in an amount of 500 ppm or less. The resin sheet comprises a resin layer and a substrate, wherein the resin layer is on the substrate and comprises the resin composition.

摘要翻译： 公开了一种复合体，该复合体的制造方法以及半导体装置，该复合体包括树脂层和在该树脂层中形成的精细布线和/或通孔，具有高粘合性和高可靠性，并且 能够高频率。 还公开了树脂组合物和树脂片，两者都可以提供这种复合体。 复合体包括树脂层和导电层，其中在树脂层的表面上具有最大宽度为1μm以上且10μm以下的槽; 导电层在槽内; 并且与导电层接触的树脂层的表面的算术平均粗糙度（Ra）为0.05μm以上且0.45μm以下，和/或其中树脂层具有直径为1μm的通孔 以上且25μm以下; 导电层在通孔内; 通孔内侧的树脂层的表面的算术平均粗糙度（Ra）为0.05μm以上且0.45μm以下。 树脂组合物包含无机填料和热固性树脂，其中无机填料含有直径大于2μm的粗颗粒的量在500ppm以下。 树脂片包括树脂层和基材，其中树脂层在基材上并包含树脂组合物。

公开(公告)号：US20110011124A1

公开(公告)日：2011-01-20

申请号：US12920853

申请日：2009-03-18

申请人： Hideki Matsuura ,  Masaru Tanaka ,  Hideki Hara

发明人： Hideki Matsuura ,  Masaru Tanaka ,  Hideki Hara

IPC分类号： F25B43/00 ,  F25B1/00

CPC分类号： C09K5/045 ,  C09K2205/126 ,  C10M171/008 ,  C10M2207/283 ,  C10M2209/04 ,  C10N2220/302 ,  F04C18/0215 ,  F04C23/008 ,  F04C2210/26 ,  F04C2210/263 ,  F25B13/00 ,  F25B2313/02331 ,  F25B2313/02741 ,  H02K3/30 ,  H02K7/14 ,  H02K9/19

摘要： A refrigeration apparatus (20) includes a refrigerant circuit (10) in which refrigerant is circulated by a compressor (30) to perform a refrigeration cycle. The compressor (30) includes a fluid machine (82) for compressing refrigerant; and an electric motor (85) for driving the fluid machine (82). Refrigerant oil having volume resistivity of equal to or greater than 1010 Ω·m at 20° C. is used for the compressor (30).

摘要翻译： 制冷装置（20）包括制冷剂回路（10），制冷剂通过压缩机（30）循环进行制冷循环。 压缩机30包括用于压缩制冷剂的流体机械82; 和用于驱动流体机械（82）的电动机（85）。 用于压缩机（30）的体积电阻率等于或大于1010且在20℃下的OHgr·m的制冷剂油被使用。

公开(公告)号：US07640388B2

公开(公告)日：2009-12-29

申请号：US10961299

申请日：2004-10-08

申请人： Katsuya Nakashima ,  Hideki Hara ,  Takashi Akai ,  Toshifumi Nomura ,  Kazumi Sato ,  Yukihisa Tsuneda ,  Toshiyuki Nishihara

发明人： Katsuya Nakashima ,  Hideki Hara ,  Takashi Akai ,  Toshifumi Nomura ,  Kazumi Sato ,  Yukihisa Tsuneda ,  Toshiyuki Nishihara

IPC分类号： G06F13/10

CPC分类号： G06F11/1435 ,  G11C13/0007 ,  G11C2213/31

摘要： A file storage apparatus capable of restoring integrity of file management information even when a power supply abnormality occurs without lowering the write speed. When updating meta data stored in an HDD, log data for reconstructing the meta data after update from the meta data before update is written into a non-volatile RAM (NVRAM), then, after this writing is completed, the update is executed. Accordingly, even when the update use meta data temporarily stored in a cache memory is partially lost due to trouble such as a power supply abnormality and when update of the meta data of a hard disk is incomplete, the log data corresponding to the meta data for the update is held in the NVRAM, so it becomes possible to restore the integrity of the meta data on the hard disk by using this log data.

摘要翻译： 即使在电源异常发生而不降低写入速度的情况下，也能够恢复文件管理信息的完整性的文件存储装置。 当更新存储在HDD中的元数据时，用于将更新后的元数据重新构建的更新前的元数据的日志数据写入非易失性RAM（NVRAM）中，则在写入完成之后，执行更新。 因此，即使当由于诸如电源异常的故障而暂时存储在高速缓冲存储器中的元数据部分地丢失，并且当硬盘的元数据的更新不完整时，即使对应于用于 该更新被保存在NVRAM中，因此可以通过使用该日志数据恢复硬盘上的元数据的完整性。

公开(公告)号：US20090293802A1

公开(公告)日：2009-12-03

申请号：US12457065

申请日：2009-06-01

申请人： Hiroaki Taguchi ,  Hideki Hara ,  Ryoichi Kaito

发明人： Hiroaki Taguchi ,  Hideki Hara ,  Ryoichi Kaito

IPC分类号： C30B15/22

CPC分类号： C30B29/06 ,  C30B15/22 ,  C30B15/305 ,  C30B30/04

摘要： By giving a shoulder portion height of at least 100 mm in growing silicon single crystals having a diameter of 450 mm (weighing up to 1100 kg) by the CZ method, it becomes possible to inhibit the occurrence of dislocations in the shoulder formation step to thereby achieve a yield improvement and increase productivity. Furthermore, when this method is applied under application of a transverse magnetic field with a predetermined intensity, the occurrence of dislocations can be further inhibited and, accordingly, defect-free silicon single crystals suited for wafer manufacture can be grown with high production efficiency. Thus, the method is best suited for the production of large-diameter silicon single crystals having a diameter of 450 mm, which are applied in the manufacture of semiconductor devices.

摘要翻译： 通过在CZ方法中生长出直径为450mm（重达1100kg）的单晶硅的肩部高度至少为100mm，可以抑制肩部形成步骤中的位错的发生，由此 实现产量提高并提高生产率。 此外，当施加具有预定强度的横向磁场的这种方法时，可以进一步抑制位错的发生，因此，可以以高生产效率生长适用于晶片制造的无缺陷硅单晶。 因此，该方法最适用于生产直径为450mm的大直径硅单晶，其应用于半导体器件的制造中。

公开(公告)号：US20070296021A1

公开(公告)日：2007-12-27

申请号：US11812325

申请日：2007-06-18

申请人： Hideki Sugiyama ,  Hideki Hara

发明人： Hideki Sugiyama ,  Hideki Hara

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A manufacturing method of a nonvolatile semiconductor memory includes steps (a) to (d). The (a) is a step of laminating a 2nd insulating film, a gate film and a hard mask film which cover a 1st gate electrode of a 1st memory cell transistor formed on a 1st region of a semiconductor substrate through a 1st insulating layer and a 3rd gate electrode of a 2nd memory cell transistor formed on a 2nd region through the 1st insulating layer. The (b) is a step of forming a 1st hard mask layer which covers a bottom portion and a side surface of a concave portion formed using the gate film between the 1st gate electrode and the 3rd gate electrode by etching the hard mask film. The (c) is a step of forming a 2nd gate electrode of the 1st memory cell transistor on the 1st region, a 4th gate electrode of the 2nd memory cell transistor on the 2nd region, and a connection layer which connects the 2nd gate electrode and the 4th gate electrode under the 1st hard mask layer by etching the gate film. The (d) is a step of exposing upper portions of the 1st gate electrode, the 3rd gate electrode and the connection layer by etching back the 2nd insulating film and the 1st hard mask layer covering a bottom portion of the concave portion to remain the 1st hard mask layer such that the 1st hard mask layer covers side surfaces of the concave portion.

摘要翻译： 非易失性半导体存储器的制造方法包括步骤（a）〜（d）。 （a）是通过第一绝缘层和第二绝缘层覆盖形成在半导体衬底的第一区域上的第一存储单元晶体管的第一栅电极的第二绝缘膜，栅极膜和硬掩模膜的步骤， 通过第一绝缘层形成在第二区域上的第二存储单元晶体管的第三栅电极。 （b）是通过蚀刻硬掩模膜形成第一硬掩模层的步骤，该第一硬掩模层覆盖在第一栅电极和第三栅电极之间使用栅极膜形成的凹部的底部和侧表面。 （c）是在第1区域形成第1存储单元晶体管的第2栅电极，在第2区域形成第二存储单元晶体管的第四栅电极的步骤，以及连接第二栅电极和 通过蚀刻栅极膜在第一硬掩模层下面的第四栅电极。 （d）是通过对第二绝缘膜和覆盖凹部的底部的第一硬掩模层进行蚀刻而使第一栅电极，第三栅电极和连接层的上部露出的步骤，以保持第一栅电极 硬掩模层，使得第一硬掩模层覆盖凹部的侧表面。

公开(公告)号：US06483195B1

公开(公告)日：2002-11-19

申请号：US09523063

申请日：2000-03-09

申请人： Hitoshi Aoki ,  Takeshi Hosomi ,  Kensuke Nakamura ,  Hideki Hara ,  Masaaki Kato

发明人： Hitoshi Aoki ,  Takeshi Hosomi ,  Kensuke Nakamura ,  Hideki Hara ,  Masaaki Kato

IPC分类号： H01L2940

CPC分类号： H01L24/11 ,  H01L21/6835 ,  H01L2221/68377 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11822 ,  H01L2224/13099 ,  H01L2224/136 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K3/062 ,  H05K3/3473 ,  H05K3/4015 ,  H01L2924/00 ,  H01L2224/05599

摘要： The invention relates to a low-cost transfer bump sheet which is capable of transferring copper-cored solder bumps with high reliability of bonding to a semiconductor chip and which is capable of transferring bumps of various structures. The invention also relates to a low-cost semiconductor flip chip in which copper-cored solder bumps with high reliability of bonding are mounted on a semiconductor chip through the use of the transfer bump sheet. In the transfer bump sheet, metal posts of two or more layers are formed on a base sheet. The invention also relates to a method of manufacturing this semiconductor flip chip, which comprises the steps of forming the base sheet on a metal foil, forming a plating mask on the metal foil, forming a first solder layer (solder coating) on the metal foil by electrolytic plating or electroless plating, removing the plating mask, and forming a metal layer (metal core) of metal posts by the etching of the metal foil through the use of the formed first solder layer (solder coating) as an etching mask.

摘要翻译： 本发明涉及一种低成本转移凸块，其能够将具有高可靠性的铜芯焊料凸块转移到半导体芯片，并且能够转移各种结构的凸块。 本发明还涉及一种低成本半导体倒装芯片，其中通过使用转移凸块来将具有高可接合性的铜芯焊料凸块安装在半导体芯片上。 在转印凸块中，在基片上形成两层以上的金属柱。 本发明还涉及一种制造该半导体倒装芯片的方法，该方法包括以下步骤：在金属箔上形成基片，在金属箔上形成电镀掩模，在金属箔上形成第一焊料层（焊料涂层） 通过电镀或化学镀，除去电镀掩模，并且通过使用所形成的第一焊料层（焊料涂层）作为蚀刻掩模，通过金属箔的蚀刻来形成金属柱的金属层（金属芯）。

公开(公告)号：US06278635B1

公开(公告)日：2001-08-21

申请号：US09726981

申请日：2000-11-30

申请人： Hideki Hara

发明人： Hideki Hara

IPC分类号： G11C1604

CPC分类号： G11C16/14 ,  G11C16/12

摘要： There is provided a storage method of a semiconductor storage apparatus provided with a source/drain area formed in a semiconductor substrate, a floating gate formed on a top layer of the area via a gate insulating film, and a control gate formed on the floating gate via an interlayer insulating film, the method comprising steps of: applying a predetermined positive voltage to a bit line connected to the drain area and a word line connected to the control gate, injecting an electron to the floating gate, and writing data to a selected memory cell; applying a predetermined negative voltage to a gate line, applying the predetermined positive voltage to a common source line connected to the semiconductor substrate or the source area, discharging the electron accumulated in the floating gate of the selected memory cell, and performing data erasing; and after the data erasing, applying the predetermined positive voltage necessary for injecting the electron to the floating gate from a channel area in the vicinity of the source area to the common source line, and performing write-back of the memory cell erased excessively.

摘要翻译： 提供了一种半导体存储装置的存储方法，该半导体存储装置设置有形成在半导体衬底中的源极/漏极区域，经由栅极绝缘膜形成在该区域的顶层上的浮置栅极和形成在浮置栅极上的控制栅极 通过层间绝缘膜，所述方法包括以下步骤：将预定的正电压施加到连接到漏极区域的位线和连接到控制栅极的字线，向浮置栅极注入电子，并将数据写入所选择的 记忆体; 将预定的负电压施加到栅极线，将预定的正电压施加到连接到半导体衬底或源极区的公共源极线，对所选择的存储单元的浮动栅极中累积的电子进行放电，并执行数据擦除; 在数据擦除之后，将从源极区附近的沟道区域向浮置栅极注入电子所需的预定正电压施加到公共源极线，并且过度地擦除存储器单元的写回。

公开(公告)号：US5977593A

公开(公告)日：1999-11-02

申请号：US975185

申请日：1997-11-20

申请人： Hideki Hara

发明人： Hideki Hara

IPC分类号： H01L21/28 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/088 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L23/62 ,  H01L29/41

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11531

摘要： A semiconductor device includes a field oxide film, a plurality of word lines, an insulating interlayer film, a plurality of contact holes, a plurality of protective diffusion layers, a plurality of common contact holes, and a plurality of metal plugs. The field oxide film is formed on a silicon substrate having one conductivity type. The word lines are formed by patterning on the field oxide film. The insulating interlayer film is formed on the field oxide film to cover the word lines. The contact holes are formed in the field oxide film to be self-aligned with the word lines. The protective diffusion layers have an opposite conductivity type and are formed on a surface of the semiconductor substrate to correspond to the contact holes. The common contact holes are formed in the insulating interlayer film to extend across the word lines and the protective diffusion layers. The common contact holes are formed at a depth to reach the protective diffusion layers while partly exposing the word lines. The metal plugs fill the common contact holes to electrically connect the protective diffusion layers and the word lines with each other. A method of manufacturing a semiconductor device is also disclosed.

摘要翻译： 半导体器件包括场氧化膜，多个字线，绝缘层间膜，多个接触孔，多个保护性扩散层，多个公共接触孔和多个金属插塞。 场氧化膜形成在具有一种导电类型的硅衬底上。 字线通过在场氧化膜上图案化而形成。 绝缘层间膜形成在场氧化膜上以覆盖字线。 接触孔形成在场氧化膜中以与字线自对准。 保护性扩散层具有相反的导电型，并且形成在半导体衬底的与接触孔相对应的表面上。 公共接触孔形成在绝缘层间膜中，以跨越字线和保护扩散层延伸。 常见的接触孔形成在深度上以到达保护性扩散层，同时部分地暴露字线。 金属插头填充公共接触孔，以将保护性扩散层和字线彼此电连接。 还公开了半导体器件的制造方法。