公开(公告)号：US20140213039A1

公开(公告)日：2014-07-31

申请号：US14150906

申请日：2014-01-09

Applicant: Chungsun LEE ,  Jung-Hwan KIM ,  Kwang-chul CHOI ,  Un-Byoung KANG ,  Jeon Il LEE

Inventor： Chungsun LEE ,  Jung-Hwan KIM ,  Kwang-chul CHOI ,  Un-Byoung KANG ,  Jeon Il LEE

IPC: H01L21/683 ,  H01L21/302

CPC classification number: H01L21/302 ,  H01L21/02057 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/92222 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2221/68304 ,  H01L21/304 ,  H01L2221/68368 ,  H01L21/78 ,  H01L2224/81

Abstract: Methods processing substrates are provided. The method may include providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting glue layer and thermosetting release layers provided on opposing sides of the thermosetting glue layer.

Abstract translation: 提供了处理衬底的方法。 该方法可以包括在衬底和载体之间提供结合层，以将衬底粘合到载体上，在衬底被载体支撑的同时处理衬底，以及去除结合层以使衬底与载体分离。 接合层可以包括热固性胶层和设置在热固性胶层的相对侧上的热固性剥离层。

公开(公告)号：US08643179B2

公开(公告)日：2014-02-04

申请号：US13240302

申请日：2011-09-22

Applicant: Yun-Hyeok Im ,  Jong-Yeon Kim ,  Tae-Je Cho ,  Un-Byoung Kang

Inventor： Yun-Hyeok Im ,  Jong-Yeon Kim ,  Tae-Je Cho ,  Un-Byoung Kang

IPC: H01L23/485

CPC classification number: H01L24/81 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/11001 ,  H01L2224/13025 ,  H01L2224/13075 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.

Abstract translation: 提供一种凸块结构，包括第一凸块和第二凸块，包括该凸块的半导体封装及其制造方法。 凸块结构包括：设置在基板的连接焊盘上的第一凸块，所述第一凸块包括从所述连接焊盘延伸的多个纳米线和连接所述多个纳米线的端部的主体; 以及设置在第一凸块的主体上的第二凸块。

公开(公告)号：US08633579B2

公开(公告)日：2014-01-21

申请号：US13208455

申请日：2011-08-12

Applicant: Un-Byoung Kang ,  Jong-Joo Lee ,  Yong-Hoon Kim ,  Tae-Hong Min

Inventor： Un-Byoung Kang ,  Jong-Joo Lee ,  Yong-Hoon Kim ,  Tae-Hong Min

IPC: H01L23/02

CPC classification number: H01L23/49827 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311

Abstract: A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line.

Abstract translation: 多芯片封装可以包括封装衬底，插入器芯片，第一半导体芯片，散热结构和第二半导体芯片。 插入器芯片可以安装在封装衬底上。 第一半导体芯片可以安装在插入器芯片上。 第一半导体芯片的尺寸可以小于插入器芯片的尺寸。 散热结构可以布置在插入器芯片上以围绕第一半导体芯片。 散热结构可以将第一半导体芯片中的热量传递到插入器芯片。 第二半导体芯片可以安装在第一半导体芯片上。 因此，可以通过散热线将第一半导体芯片中的热量有效地传递到插入器芯片。

公开(公告)号：US08592991B2

公开(公告)日：2013-11-26

申请号：US13235369

申请日：2011-09-17

Applicant: Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

Inventor： Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/00

CPC classification number: H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Abstract translation: 在一个实施例中，半导体器件包括具有第一表面的半导体衬底和与第一表面相对的第二表面。 第二表面限定再分布沟槽。 基板具有贯穿其中的通孔。 半导体器件还包括设置在通孔中的贯通孔。 通孔可以包括依次形成在通孔的内壁上的通孔绝缘层，阻挡层。 通孔还可以包括邻近阻挡层的导电连接器。 半导体器件还包括形成在衬底的第二表面上的绝缘层图案。 绝缘层图案限定了暴露通孔的顶表面的区域的开口。 半导体器件包括设置在沟槽中并与通孔电连接的再分配层。 绝缘层图案与导电连接器的区域重叠。

公开(公告)号：US20120156823A1

公开(公告)日：2012-06-21

申请号：US13281870

申请日：2011-10-26

Applicant: Jong-Yun MYUNG ,  Hyuek-Jae Lee ,  Ji-Sun Hong ,  Tae-Je Cho ,  Un-Byoung Kang ,  Hyung-Sun Jang ,  Eun-Mi Kim ,  Jung-Hwan Kim ,  Tae-Hong Min

Inventor： Jong-Yun MYUNG ,  Hyuek-Jae Lee ,  Ji-Sun Hong ,  Tae-Je Cho ,  Un-Byoung Kang ,  Hyung-Sun Jang ,  Eun-Mi Kim ,  Jung-Hwan Kim ,  Tae-Hong Min

IPC: H01L31/18 ,  H01L21/50 ,  H01L21/78

CPC classification number: H01L21/78 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/1464 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12043 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00

Abstract: A method of forming a semiconductor device includes preparing a semiconductor substrate having a plurality of chips formed thereon and a scribe lane disposed between the chips, simultaneously forming a groove having a first depth in the scribe lane, and a through hole penetrating the chips and having a second depth. The chips are separated along the groove. The first depth is smaller than the second depth.

Abstract translation: 一种形成半导体器件的方法包括制备其上形成有多个芯片的半导体衬底和设置在芯片之间的划线，同时形成在划线中具有第一深度的凹槽，以及穿透芯片的通孔，并具有 第二个深度。 芯片沿凹槽分开。 第一深度小于第二深度。

公开(公告)号：US08125042B2

公开(公告)日：2012-02-28

申请号：US12617910

申请日：2009-11-13

Applicant: Jung-Hwan Kim ,  Un-Byoung Kang ,  Dong-Hun Yi ,  Woonseong Kwon ,  Hyung-Sun Jang ,  Jongkeun Jeon ,  Yongjin Lee ,  Keeseok Kim

Inventor： Jung-Hwan Kim ,  Un-Byoung Kang ,  Dong-Hun Yi ,  Woonseong Kwon ,  Hyung-Sun Jang ,  Jongkeun Jeon ,  Yongjin Lee ,  Keeseok Kim

IPC: H01L33/00 ,  H01L31/0232

CPC classification number: H01L27/14618 ,  H01L27/14627 ,  H01L27/14632 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package includes a semiconductor chip, a transparent substrate, an adhesive pattern, and at least one dew-proofer. The semiconductor includes a pixel area. The transparent substrate is disposed on the semiconductor chip. The adhesive pattern is disposed between the semiconductor chip and the transparent substrate and provides a space on the pixel area. At least one dew-proofer is disposed between the semiconductor chip and the transparent substrate and spaced from the adhesive pattern.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括半导体芯片，透明基板，粘合剂图案和至少一个露水开发器。 半导体包括像素区域。 透明基板设置在半导体芯片上。 粘合剂图案设置在半导体芯片和透明基板之间，并且在像素区域上提供空间。 在半导体芯片和透明基板之间设置至少一个露水器，并且与粘合剂图案间隔开。

公开(公告)号：US08089145B1

公开(公告)日：2012-01-03

申请号：US12272606

申请日：2008-11-17

Applicant: Gwang Ho Kim ,  Jin Seong Kim ,  Dong Joo Park ,  Dae Byoung Kang

Inventor： Gwang Ho Kim ,  Jin Seong Kim ,  Dong Joo Park ,  Dae Byoung Kang

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/495 ,  H01L23/02 ,  H01L29/40 ,  H01L23/28

CPC classification number: H01L23/49541 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/49517 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads are provided in two concentric rows or rings which at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, and the semiconductor die are encapsulated by the package body.

Abstract translation: 根据本发明，提供了包括唯一配置的引线框的半导体封装（例如，QFP封装），其尺寸和配置为使半导体封装中的暴露引线的可用数量最大化。 更具体地，本发明的半导体封装包括限定多个周边边缘段的大致平面的管芯焊盘或管芯焊盘。 此外，半导体封装包括多个引线。 这些引线中的一些以两个同心的行或环提供，其至少部分地绕过管芯焊盘，其他引线包括从半导体封装的封装主体的相应侧表面突出的部分。 连接到管芯焊盘的顶表面的是至少一个半导体管芯，其电连接到至少一些引线。 芯片焊盘，引线和半导体管芯的至少一部分被封装体封装。

公开(公告)号：US07893514B2

公开(公告)日：2011-02-22

申请号：US11831768

申请日：2007-07-31

Applicant: Woon-Seong Kwon ,  Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Hyung-Sun Jang

Inventor： Woon-Seong Kwon ,  Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Hyung-Sun Jang

IPC: H01L31/0203 ,  H01L31/0232 ,  H01L23/02 ,  H01L21/00

CPC classification number: H01L27/14618 ,  H01L24/97 ,  H01L27/14625 ,  H01L27/14683 ,  H01L27/14685 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An image sensor package, a method of manufacturing the same, and an image sensor module including the image sensor package are provided. In the image sensor package, an image sensor chip is installed onto a depression of a transmissive substrate. An adhesive bonds the image sensor chip to the transmissive substrate and seals an Active Pixel Sensor (APS) on the image sensor chip, protecting it from fine particle contamination. An IR cutting film is disposed on the transmissive substrate to minimize the height of the image sensor package. The image sensor package is electrically connected to external connection pads in the depression. Consequently, the image sensor package has a minimum height, is not susceptible to particle contamination, and does not require expensive alignment processes during manufacturing.

Abstract translation: 提供了图像传感器封装，其制造方法和包括图像传感器封装的图像传感器模块。 在图像传感器封装中，将图像传感器芯片安装在透光性基板的凹部上。 粘合剂将图像传感器芯片粘合到透射基板上，并将图像传感器芯片上的有源像素传感器（APS）密封并保护其免受细颗粒污染。 将IR切割膜设置在透射基底上以最小化图像传感器封装的高度。 图像传感器封装电连接到凹陷中的外部连接焊盘。 因此，图像传感器封装具有最小高度，不易受到颗粒污染，并且在制造期间不需要昂贵的对准过程。

公开(公告)号：US07786581B2

公开(公告)日：2010-08-31

申请号：US12073310

申请日：2008-03-04

Applicant: Un Byoung Kang ,  Yong Hwan Kwon ,  Chung Sun Lee ,  Woon Seong Kwon ,  Hyung Sun Jang

Inventor： Un Byoung Kang ,  Yong Hwan Kwon ,  Chung Sun Lee ,  Woon Seong Kwon ,  Hyung Sun Jang

IPC: H01L23/48

CPC classification number: H01L24/83 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11901 ,  H01L2224/11912 ,  H01L2224/13099 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/01007 ,  H01L2924/01028 ,  H01L2224/29099 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, and a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成扩散阻挡层，并在衬底上形成至少两个特征，使得扩散阻挡层分别设置在每个特征和衬底之间，并接触至少两个特征。 衬底的第一杂质区包含第一类杂质，衬底的第二杂质区包含不同于第一类型的第二类杂质，所述至少两个特征的第一特征在第一杂质区， 并且所述至少两个特征的第二特征在于第二杂质区域，使得第二特征通过不同的杂质区域与第一特征电隔离。

公开(公告)号：US07619315B2

公开(公告)日：2009-11-17

申请号：US11952426

申请日：2007-12-07

Applicant: Woon-Seong Kwon ,  Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Hyung-Sun Jang

Inventor： Woon-Seong Kwon ,  Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Hyung-Sun Jang

IPC: H01L21/56

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L27/14618 ,  H01L31/0203 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A stack type semiconductor chip package includes a first wafer mold, a protection substrate, and a second wafer mold that are stacked in a wafer level process. The first wafer mold includes a first chip having first pads and a first mold layer encapsulating the first chip. The protection substrate is placed on the first wafer mold, is mechanically bonded with the first wafer mold using a first adhesive layer, and includes wiring layers facing the first pads. The second wafer mold is placed under the first wafer mold, is mechanically bonded with the first wafer mold using a second adhesive layer, and includes a second chip having second pads, and a second mold layer encapsulating the second chip. First vias electrically connect the wiring layers of the protection substrate with the second pads. Second vias electrically connect the wiring layers of the protection substrate with external connection terminals.

Abstract translation: 堆叠型半导体芯片封装包括在晶片级工艺中堆叠的第一晶片模具，保护基板和第二晶片模具。 第一晶片模具包括具有第一焊盘的第一芯片和封装第一芯片的第一模具层。 保护基板被放置在第一晶片模具上，使用第一粘合剂层与第一晶片模具机械结合，并且包括面向第一焊盘的布线层。 第二晶片模具放置在第一晶片模具下面，使用第二粘合剂层与第一晶片模具机械结合，并且包括具有第二焊盘的第二芯片和封装第二芯片的第二模具层。 第一通孔将保护衬底的布线层与第二衬垫电连接。 第二通孔将保护基板的布线层与外部连接端子电连接。