公开(公告)号：US10157766B2

公开(公告)日：2018-12-18

申请号：US15112429

申请日：2014-03-19

申请人： Un-Byoung Kang ,  Joonsik Sohn ,  Jung-Seok Ahn ,  Chungsun Lee ,  Taeje Cho

发明人： Un-Byoung Kang ,  Joonsik Sohn ,  Jung-Seok Ahn ,  Chungsun Lee ,  Taeje Cho

IPC分类号： H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L23/544 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

摘要： Provided are methods of fabricating a semiconductor device. According to the method, a first glue layer, a first release layer, a second glue layer, and a second release layer may be sequentially interposed between a carrier and a device wafer. All of the first glue layer, the first release layer, the second glue layer, and the second release layer may be formed of thermosetting resin.

公开(公告)号：US09905550B2

公开(公告)日：2018-02-27

申请号：US14736247

申请日：2015-06-10

申请人： Sang-Uk Han ,  Seungwon Park ,  Un-Byoung Kang ,  Taeje Cho

发明人： Sang-Uk Han ,  Seungwon Park ,  Un-Byoung Kang ,  Taeje Cho

IPC分类号： H01L21/00 ,  H01L25/00 ,  H01L21/82 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/82 ,  H01L23/3128 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/00

摘要： Embodiments of the inventive concepts provide a semiconductor package and a method of fabricating the same. The method includes forming a groove to separate first semiconductor chips from each other. Forming the groove include performing a first sawing process on a bottom surface of a semiconductor substrate to cut the semiconductor substrate and a portion of a mold layer in a direction inclined with respect to the bottom surface, and performing a second sawing process to cut the mold layer in a direction substantially perpendicular to the bottom surface of the semiconductor substrate. A minimum width of the groove formed in the semiconductor substrate by the first sawing process may be greater than a width of the groove formed in the mold layer by the second sawing process.

公开(公告)号：US20160233155A1

公开(公告)日：2016-08-11

申请号：US15130904

申请日：2016-04-15

申请人： Ho-Jin LEE ,  Tae-Je CHO ,  Dong-Hyeon JANG ,  Ho-Geon SONG ,  Se-Young JEONG ,  Un-Byoung KANG ,  Min-Seung YOON

发明人： Ho-Jin LEE ,  Tae-Je CHO ,  Dong-Hyeon JANG ,  Ho-Geon SONG ,  Se-Young JEONG ,  Un-Byoung KANG ,  Min-Seung YOON

IPC分类号： H01L23/498 ,  H01L23/48

CPC分类号： H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

摘要翻译： 在一个实施例中，半导体器件包括具有第一表面的半导体衬底和与第一表面相对的第二表面。 第二表面限定再分布沟槽。 基板具有贯穿其中的通孔。 半导体器件还包括设置在通孔中的贯通孔。 通孔可以包括依次形成在通孔的内壁上的通孔绝缘层，阻挡层。 通孔还可以包括邻近阻挡层的导电连接器。 半导体器件还包括形成在衬底的第二表面上的绝缘层图案。 绝缘层图案限定了暴露通孔的顶表面的区域的开口。 半导体器件包括设置在沟槽中并与通孔电连接的再分配层。 绝缘层图案与导电连接器的区域重叠。

公开(公告)号：US08563349B2

公开(公告)日：2013-10-22

申请号：US13281870

申请日：2011-10-26

申请人： Jong-Yun Myung ,  Hyuek-Jae Lee ,  Ji-Sun Hong ,  Tae-Je Cho ,  Un-Byoung Kang ,  Hyung-Sun Jang ,  Eun-Mi Kim ,  Jung-Hwan Kim ,  Tae-Hong Min

发明人： Jong-Yun Myung ,  Hyuek-Jae Lee ,  Ji-Sun Hong ,  Tae-Je Cho ,  Un-Byoung Kang ,  Hyung-Sun Jang ,  Eun-Mi Kim ,  Jung-Hwan Kim ,  Tae-Hong Min

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/1464 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12043 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00

摘要： A method of forming a semiconductor device includes preparing a semiconductor substrate having a plurality of chips formed thereon and a scribe lane disposed between the chips, simultaneously forming a groove having a first depth in the scribe lane, and a through hole penetrating the chips and having a second depth. The chips are separated along the groove. The first depth is smaller than the second depth.

摘要翻译： 一种形成半导体器件的方法包括制备其上形成有多个芯片的半导体衬底和设置在芯片之间的划线，同时形成在划线中具有第一深度的凹槽，以及穿透芯片的通孔，并具有 第二个深度。 芯片沿凹槽分开。 第一深度小于第二深度。

公开(公告)号：US20120119359A1

公开(公告)日：2012-05-17

申请号：US13240302

申请日：2011-09-22

申请人： Yun-Hyeok Im ,  Jong-Yeon Kim ,  Tae-Je Cho ,  Un-Byoung Kang

发明人： Yun-Hyeok Im ,  Jong-Yeon Kim ,  Tae-Je Cho ,  Un-Byoung Kang

IPC分类号： H01L23/485

CPC分类号： H01L24/81 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/11001 ,  H01L2224/13025 ,  H01L2224/13075 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00

摘要： Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.

摘要翻译： 提供一种凸块结构，包括第一凸块和第二凸块，包括该凸块的半导体封装及其制造方法。 凸块结构包括：设置在基板的连接焊盘上的第一凸块，所述第一凸块包括从所述连接焊盘延伸的多个纳米线和连接所述多个纳米线的端部的主体; 以及设置在第一凸块的主体上的第二凸块。

公开(公告)号：US07948555B2

公开(公告)日：2011-05-24

申请号：US12254354

申请日：2008-10-20

申请人： Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Woon-Seong Kwon ,  Hyung-Sun Jang

发明人： Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Woon-Seong Kwon ,  Hyung-Sun Jang

IPC分类号： H04N5/225 ,  H04N9/077 ,  H01L31/0232

CPC分类号： H04N5/2254 ,  H01L27/14618 ,  H01L2924/0002 ,  H04N5/2253 ,  H04N5/2257 ,  H04N2007/145 ,  H01L2924/00

摘要： A camera module includes an image sensor chip, a lens structure, a transparent substrate, an adhesive portion, and a light blocking layer. The image sensor chip includes a light receiving area and a circuit area. The lens structure is positioned on the image sensor chip and configured to allow light to enter the image sensor chip. The transparent substrate is positioned between the image sensor chip and the lens structure, the transparent substrate allowing light from the lens structure to enter the light receiving area. The adhesive portion attaches the image sensor chip and the transparent substrate, and covers the circuit area. The light blocking layer is attached to the transparent substrate to block light from entering the circuit area.

摘要翻译： 相机模块包括图像传感器芯片，透镜结构，透明基板，粘合部分和遮光层。 图像传感器芯片包括光接收区域和电路区域。 透镜结构位于图像传感器芯片上并且被配置为允许光进入图像传感器芯片。 透明基板位于图像传感器芯片和透镜结构之间，透明基板允许来自透镜结构的光进入光接收区域。 粘合剂部附着图像传感器芯片和透明基板，并且覆盖电路区域。 遮光层附着到透明基板上以阻挡光线进入电路区域。

公开(公告)号：US20100117181A1

公开(公告)日：2010-05-13

申请号：US12617910

申请日：2009-11-13

申请人： Jung-Hwan Kim ,  Un-Byoung Kang ,  Dong-Hun Yi ,  Woonseong Kwon ,  Hyung-Sun Jang ,  Jongkeun Jeon ,  Yongjin Lee ,  Keeseok Kim

发明人： Jung-Hwan Kim ,  Un-Byoung Kang ,  Dong-Hun Yi ,  Woonseong Kwon ,  Hyung-Sun Jang ,  Jongkeun Jeon ,  Yongjin Lee ,  Keeseok Kim

IPC分类号： H01L31/0232 ,  H01L31/02

CPC分类号： H01L27/14618 ,  H01L27/14627 ,  H01L27/14632 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

摘要： Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package includes a semiconductor chip, a transparent substrate, an adhesive pattern, and at least one dew-proofer. The semiconductor includes a pixel area. The transparent substrate is disposed on the semiconductor chip. The adhesive pattern is disposed between the semiconductor chip and the transparent substrate and provides a space on the pixel area. At least one dew-proofer is disposed between the semiconductor chip and the transparent substrate and spaced from the adhesive pattern.

摘要翻译： 提供半导体封装及其制造方法。 半导体封装包括半导体芯片，透明基板，粘合剂图案和至少一个露水开发器。 半导体包括像素区域。 透明基板设置在半导体芯片上。 粘合剂图案设置在半导体芯片和透明基板之间，并且在像素区域上提供空间。 在半导体芯片和透明基板之间设置至少一个露水器，并且与粘合剂图案间隔开。

公开(公告)号：US20090122178A1

公开(公告)日：2009-05-14

申请号：US12254354

申请日：2008-10-20

申请人： Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Woon-Seong KWON ,  Hyung-Sun JANG

发明人： Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Woon-Seong KWON ,  Hyung-Sun JANG

IPC分类号： H04N5/225

CPC分类号： H04N5/2254 ,  H01L27/14618 ,  H01L2924/0002 ,  H04N5/2253 ,  H04N5/2257 ,  H04N2007/145 ,  H01L2924/00

摘要： A camera module includes an image sensor chip, a lens structure, a transparent substrate, an adhesive portion, and a light blocking layer. The image sensor chip includes a light receiving area and a circuit area. The lens structure is positioned on the image sensor chip and configured to allow light to enter the image sensor chip. The transparent substrate is positioned between the image sensor chip and the lens structure, the transparent substrate allowing light from the lens structure to enter the light receiving area. The adhesive portion attaches the image sensor chip and the transparent substrate, and covers the circuit area. The light blocking layer is attached to the transparent substrate to block light from entering the circuit area.

摘要翻译： 相机模块包括图像传感器芯片，透镜结构，透明基板，粘合部分和遮光层。 图像传感器芯片包括光接收区域和电路区域。 透镜结构位于图像传感器芯片上并且被配置为允许光进入图像传感器芯片。 透明基板位于图像传感器芯片和透镜结构之间，透明基板允许来自透镜结构的光进入光接收区域。 粘合剂部附着图像传感器芯片和透明基板，并且覆盖电路区域。 遮光层附着到透明基板上以阻挡光线进入电路区域。

公开(公告)号：US20080169546A1

公开(公告)日：2008-07-17

申请号：US11952426

申请日：2007-12-07

申请人： Woon-Seong KWON ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

发明人： Woon-Seong KWON ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

IPC分类号： H01L23/488 ,  H01L21/56

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L27/14618 ,  H01L31/0203 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A stack type semiconductor chip package includes a first wafer mold, a protection substrate, and a second wafer mold that are stacked in a wafer level process. The first wafer mold includes a first chip having first pads and a first mold layer encapsulating the first chip. The protection substrate is placed on the first wafer mold, is mechanically bonded with the first wafer mold using a first adhesive layer, and includes wiring layers facing the first pads. The second wafer mold is placed under the first wafer mold, is mechanically bonded with the first wafer mold using a second adhesive layer, and includes a second chip having second pads, and a second mold layer encapsulating the second chip. First vias electrically connect the wiring layers of the protection substrate with the second pads. Second vias electrically connect the wiring layers of the protection substrate with external connection terminals.

摘要翻译： 堆叠型半导体芯片封装包括在晶片级工艺中堆叠的第一晶片模具，保护基板和第二晶片模具。 第一晶片模具包括具有第一焊盘的第一芯片和封装第一芯片的第一模具层。 保护基板被放置在第一晶片模具上，使用第一粘合剂层与第一晶片模具机械结合，并且包括面向第一焊盘的布线层。 第二晶片模具放置在第一晶片模具下面，使用第二粘合剂层与第一晶片模具机械结合，并且包括具有第二焊盘的第二芯片和封装第二芯片的第二模具层。 第一通孔将保护衬底的布线层与第二衬垫电连接。 第二通孔将保护基板的布线层与外部连接端子电连接。

公开(公告)号：US20160013174A1

公开(公告)日：2016-01-14

申请号：US14736247

申请日：2015-06-10

申请人： Sang-Uk HAN ,  Seungwon PARK ,  Un-Byoung KANG ,  Taeje CHO

发明人： Sang-Uk HAN ,  Seungwon PARK ,  Un-Byoung KANG ,  Taeje CHO

IPC分类号： H01L25/00 ,  H01L21/82 ,  H01L23/48 ,  H01L21/56

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/82 ,  H01L23/3128 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/00

摘要： Embodiments of the inventive concepts provide a semiconductor package and a method of fabricating the same. The method includes forming a groove to separate first semiconductor chips from each other. Forming the groove include performing a first sawing process on a bottom surface of a semiconductor substrate to cut the semiconductor substrate and a portion of a mold layer in a direction inclined with respect to the bottom surface, and performing a second sawing process to cut the mold layer in a direction substantially perpendicular to the bottom surface of the semiconductor substrate. A minimum width of the groove formed in the semiconductor substrate by the first sawing process may be greater than a width of the groove formed in the mold layer by the second sawing process.

摘要翻译： 本发明构思的实施例提供一种半导体封装及其制造方法。 该方法包括形成沟槽以将第一半导体芯片彼此分开。 形成凹槽包括在半导体衬底的底表面上执行第一锯切工艺以在相对于底表面倾斜的方向上切割半导体衬底和模具层的一部分，并且执行第二锯切工艺以切割模具 层在基本上垂直于半导体衬底的底表面的方向上。 通过第一锯切工艺在半导体衬底中形成的槽的最小宽度可以大于通过第二锯切工艺在模具层中形成的槽的宽度。