公开(公告)号：US5384476A

公开(公告)日：1995-01-24

申请号：US62333

申请日：1987-06-09

Applicant: Jun-ichi Nishizawa ,  Tadahiro Ohmi

Inventor： Jun-ichi Nishizawa ,  Tadahiro Ohmi

IPC: H01L23/556 ,  H01L27/108 ,  H01L29/10 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L23/556 ,  H01L27/10808 ,  H01L29/105 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/7722 ,  H01L29/78 ,  H01L2924/0002

Abstract: A semiconductor device having a source region, a drain region and a channel region which are formed in a surface portion of a semiconductor substrate, and a gate formed with a material having a relatively high built-in voltage relative to the source region. This semiconductor device may further include, in the semiconductor substrate to extend along the channel region, a highly-doped region having a conductivity type opposite to that of the source region. This highly-closed region may have an impurity concentration gradient which is greater toward its portion facing the abovesaid surface of the substrate. These arrangements serve to prevent extinction of memory due to current leakage during absence of bias voltage which otherwise would develop in semiconductor devices having short-channel and thin gate oxide layer, and due to irradiation of alpha-particle onto the device.

Abstract translation: 具有形成在半导体基板的表面部分中的源极区域，漏极区域和沟道区域的半导体器件和形成有相对于源极区域具有相对较高内置电压的材料的栅极。 该半导体器件还可以在半导体衬底中沿沟道区域延伸具有与源极区域相反的导电类型的高掺杂区域。 这个高度封闭的区域可以具有对其面向衬底的上述表面的部分更大的杂质浓度梯度。 这些布置用于防止由于不存在偏置电压时的电流泄漏而导致的存储器的消光，否则将在具有短沟道和薄栅极氧化物层的半导体器件中以及由于α粒子照射到器件上而产生。

公开(公告)号：US5373808A

公开(公告)日：1994-12-20

申请号：US50325

申请日：1993-05-19

Applicant: Koichi Sassa ,  Takashi Atami ,  Keiji Shirata

Inventor： Koichi Sassa ,  Takashi Atami ,  Keiji Shirata

IPC: C30B15/00 ,  C30B15/02 ,  C30B15/22

CPC classification number: C30B15/02 ,  C30B15/00 ,  C30B29/42 ,  Y10T117/1032 ,  Y10T117/1064

Abstract: An apparatus and a method are presented for preparing a single crystal ingot of a compound semiconductor material which contains a high vapor pressure component. The apparatus includes: a furnace housing 78 housing a cylindrical hermetic vessel 20 having a ceiling plate section 22A and a bottom plate section 42. External heaters 36, 38 and 40 surrounding the hermetic vessel 20, and a vapor pressure control section which communicates hermetically with the vessel 20. The vapor pressure control section includes: a vapor pressure control tube 98 having a hermetic inner space formed between an inner wall 102 and a coaxial outer wall 100; a communication conduit 96 which hermetically communicates the inner space of the vapor pressure control tube 98 with the inner space of the vessel 20; heat pipes 108, 112 extending along at least one of either the inner wall or the outer wall; control heaters 110, 114 disposed both on the inside of the inner wall and on the outside of the outer wall of the vapor pressure control section 98.

Abstract translation: PCT No.PCT / JP91 / 01547 Sec。 371日期：1993年5月19日 102（e）日期1993年5月19日PCT 1991年11月12日PCT PCT。 出版物WO93 / 22040 日期为1993年11月11日。提出了一种制备含有高蒸汽压成分的化合物半导体材料的单晶锭的装置和方法。 该装置包括：炉壳78，其容纳具有顶板部分22A和底板部分42的圆柱形密封容器20.围绕密封容器20的外部加热器36,38和40以及气密控制部分 蒸汽压力控制部分包括：蒸汽压力控制管98，其具有形成在内壁102和同轴外壁100之间的气密内部空间; 将蒸气压控制管98的内部空间与容器20的内部空间气密地连通的连通导管96; 沿着内壁或外壁中的至少一个延伸的热管108,112; 控制加热器110,114设置在蒸汽压控制部分98的内壁的内侧和外壁上。

公开(公告)号：US5065206A

公开(公告)日：1991-11-12

申请号：US301334

申请日：1989-01-25

Applicant: Jun-Ichi Nishizawa ,  Takashige Tamamushi ,  Hideo Maeda

Inventor： Jun-Ichi Nishizawa ,  Takashige Tamamushi ,  Hideo Maeda

IPC: H01L27/146 ,  H01L31/0248

CPC classification number: H01L27/14679

Abstract: A semiconductor device comprises a semiconductive substrate of a low impurity concentration, a channel area of a low impurity concentration formed on the substrate, a source area formed on the channel area and having a high impurity concentration of a conductive type opposite to that of the substrate, a drain area formed on the channel area and having a high impurity concentration of a conductive type opposite to that of the substrate, and an accumulating gate area formed on the channel area and having a conductive type same as that of the substrate. The source area and drain area are arranged in a predetermined direction along the substrate. The accumulating gate area comprises a first part sandwiched between the source area and the drain area and extended in a direction crossing the predetermined direction and second and third parts connected with the first part and approximately extended in the predetermined direction. The accumulating gate area is adapted to accumulate a charge corresponding to the intensity of the incident radiation. A current flows from one to the other of the source area and the drain area through a part of the channel area sandwiched between the first part of the accumulating gate area and the substrate. The potential of the accumulating gate area varies according to the accumulated charge. The current varies according to the potential of the accumulating gate area.

Abstract translation: 半导体器件包括低杂质浓度的半导体衬底，形成在衬底上的低杂质浓度的沟道面积，形成在沟道区上的源极区，并且具有与衬底相反的导电类型的高杂质浓度 形成在沟道区上并且具有与衬底相反的导电类型的高杂质浓度的漏极区和形成在沟道区上并且具有与衬底相同的导电类型的积聚栅极区。 源极区域和漏极区域沿着衬底沿预定方向布置。 蓄积栅极区域包括夹在源极区域和漏极区域之间并沿与预定方向交叉的方向延伸的第一部分，以及与第一部分连接并且沿预定方向大致延伸的第二和第三部分。 累积栅极区域适于累积对应于入射辐射强度的电荷。 通过夹在积聚栅极区域的第一部分和基板之间的沟道区域的一部分，电流从源极区域和漏极区域中的一个流入另一个。 蓄积栅极区域的电位根据累积电荷而变化。 电流根据蓄电池区域的电位而变化。

公开(公告)号：US4994872A

公开(公告)日：1991-02-19

申请号：US225870

申请日：1988-07-29

Applicant: Jun-ichi Nishizawa ,  Tadahiro Ohmi

Inventor： Jun-ichi Nishizawa ,  Tadahiro Ohmi

IPC: H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423 ,  H01L29/772 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L27/0225 ,  H01L27/0883 ,  H01L27/092 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/7722 ,  H01L29/7801 ,  H01L29/4236 ,  H01L29/42368

Abstract: An insulated-gate static induction transistor is formed by establishing a potential barrier in a semiconductor region of one conductivity type between the source and the drain regions of the other conductivity type. The height of the potential barrier should be sensitive to the drain voltage as well as to the gate voltage. Therefore, the semiconductor region should have a low impurity concentration and short length. The potential barrier can be established by varying the field effect of the gate voltage in the semiconductor region and/or by the built-in potential between the source region and the semiconductor region.

公开(公告)号：US4985738A

公开(公告)日：1991-01-15

申请号：US939259

申请日：1986-12-05

Applicant: Jun-ichi Nishizawa ,  Tadahiro Ohmi

Inventor： Jun-ichi Nishizawa ,  Tadahiro Ohmi

IPC: H01L29/739

CPC classification number: H01L29/7392

Abstract: A semiconductor thyristor of the Static Induction type having a split-gate structure, e.g., driving gates and non-driving gates, for controlling cathode-anode current flow. The split-gate structure comprises a plurality of primary gates formed in recesses of the channel region which respond to an external control signal for providing primary current control, and a plurality of secondary non-driving gates which are influenced by electric fields in the channel region extant during thyristor operation for providing secondary current control. In operation, the driving and non-driving gates coact so that the non-driving gates, having an induced potential lower than the potential applied to the driving gates, absorb charge carriers injected in the channel during thyristor operation. The relative disposition of the non-driving gates and the anode, as well as the respective doping concentrations of the anode and channel regions, enable the non-driving gates to absorb a substantial portion of charge carriers injected from the anode into the channel during high-power operation. Fast turn-on and turn-off is achieved by exclusion of the non-driving gate capacitance in the driving gate circuit.

Abstract translation: 具有用于控制阴极 - 阳极电流的具有分离栅极结构（例如驱动栅极和非驱动栅极）的静态感应型的半导体晶闸管。 分离栅极结构包括形成在沟道区的凹部中的多个主栅极，其响应于用于提供初级电流控制的外部控制信号，以及受到沟道区域中的电场影响的多个次级非驱动栅极 在晶闸管操作期间提供二次电流控制。 在操作中，驱动和非驱动栅极共同作用，使得具有低于施加到驱动栅极的电位的感应电位的非驱动栅极在晶闸管操作期间吸收在沟道中注入的电荷载流子。 非驱动栅极和阳极的相对配置以及阳极和沟道区域的各自的掺杂浓度使得非驱动栅极能够在高的期间吸收从阳极注入到沟道中的大部分电荷载流子 电力操作。 通过排除驱动门电路中的非驱动栅极电容来实现快速导通和关断。

公开(公告)号：US4939571A

公开(公告)日：1990-07-03

申请号：US082979

申请日：1987-08-04

Applicant: Jun-ichi Nishizawa ,  Tadahiro Ohmi

Inventor： Jun-ichi Nishizawa ,  Tadahiro Ohmi

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/772 ,  H01L29/78 ,  H01L29/80 ,  H03K19/091

CPC classification number: H03K19/0912 ,  H01L27/0883 ,  H01L27/092 ,  H01L29/7722 ,  H01L29/7835

Abstract: An insulated-gate type transistor having a semi-conductor body of a low impurity concentration, a heavily-doped source region of a conductivity type opposite to that of the semiconductor body for supplying charge carriers, a heavily-doped drain region for receiving the carriers supplied from the source region, both of which regions may be provided separately in a main surface of the body, a channel region located between the source and drain regions for the travel of these carriers, an insulated-gate structure inputted with a gate voltage for controlling the travel of those carriers, a semiconductor region formed in the neighborhood of the source region within the body and having a portion located below the source region and another portion extending beyond therefrom toward the drain region and serving to define the channel region and to increase the ratio of the amount of carriers reaching the drain region to the total amount of the carriers supplied from the source region. This transistor can be easily manufactured with a single substrate from that side of the main surface. This transistor is suitable for use in constructing integrated circuits and enables construction of complementary devices.

Abstract translation: 一种具有低杂质浓度的半导体体的绝缘栅型晶体管，具有与用于提供电荷载流子的半导体本体相反的导电类型的重掺杂源极区，用于接收载流子的重掺杂漏极区 从源极区域提供的两个区域可以分别设置在主体的主表面中，位于源极和漏极区之间的沟道区域用于这些载流子的行进，输入栅极电压的绝缘栅极结构 控制这些载体的行进，形成在体内源区域附近的半导体区域，并且具有位于源极区域下方的部分和从其延伸超过其的部分朝向漏极区域并且用于限定沟道区域并增加 到达漏极区的载流子的量与从源极区域供给的载流子的总量的比率。 该晶体管可以容易地从主表面的那一侧用单个衬底制造。 该晶体管适用于构建集成电路，并可构建互补器件。

公开(公告)号：US4783426A

公开(公告)日：1988-11-08

申请号：US124390

申请日：1987-11-19

Applicant: Jun-ichi Nishizawa

Inventor： Jun-ichi Nishizawa

IPC: C30B19/04 ,  H01L21/208 ,  H01L21/368 ,  H01L33/28

CPC classification number: H01L33/28 ,  C30B19/04 ,  C30B29/48 ,  H01L21/02409 ,  H01L21/02551 ,  H01L21/0256 ,  H01L21/02579 ,  H01L21/02581 ,  H01L21/02625 ,  H01L21/02628 ,  H01L33/0083

Abstract: A semiconductor device made of a II-VI compound semiconductor and having a p type semiconductor crystal. The p type semiconductor crystal is one obtained by growing the II-VI compound semiconductor crystal by relying on a liquid phase crystal growth process using a solvent comprised of one of Group II and Group VI elements constituting the Group II-VI compound semiconductor and having a higher vapor pressure over the other of these elements in an atmosphere comprised of the other of the elements having a lower vapor pressure under controlled vapor pressure of the atmosphere, and by doping into the solvent a p type impurity element selected from Group Ia and Ib elements in an amount of a range from 1.times.10.sup.-3 to 5.times.10.sup.-1 mol %. Thus, p type semiconductor crystals for use in semiconductor devices can be obtained easily from II-VI compound semiconductors. The present invention is especially effective in ZnSe crystals.

Abstract translation: 一种由II-VI化合物半导体制成且具有p型半导体晶体的半导体器件。 p型半导体晶体是通过使用由构成II-VI族化合物半导体的II族和VI族元素之一的溶剂依赖于液相晶体生长工艺来生长II-VI族化合物半导体晶体而得到的，具有 在气氛中受控蒸气压下具有较低蒸汽压的另一元素组成的气氛中，另外一种元素的蒸气压较高，并且掺杂到选自Ia和Ib族元素中的溶剂型p型杂质元素 其量为1×10 -3至5×10 -1 mol％。 因此，可以容易地从II-VI化合物半导体获得用于半导体器件的p型半导体晶体。 本发明在ZnSe晶体中特别有效。

公开(公告)号：US4608582A

公开(公告)日：1986-08-26

申请号：US515462

申请日：1983-07-20

Applicant: Jun-ichi Nishizawa

Inventor： Jun-ichi Nishizawa

IPC: H01L21/762 ,  H01L21/763 ,  H01L27/02 ,  H01L27/07 ,  H01L29/739 ,  H01L29/80

CPC classification number: H01L21/76224 ,  H01L21/76232 ,  H01L21/763 ,  H01L27/0225 ,  H01L27/0716 ,  H01L27/0722 ,  H01L29/739

Abstract: The new kind of field effect transistor having a non-saturating characteristic, i.e. static induction transistor (SIT), proposed by the present inventor is modified to serve as a substitute of any conventional bipolar transistor in a given circuitry. That is, the gate-to-gate distance and the impurity concentration of the channel region of an SIT are so selected that the channel is pinched off by the depletion layer at a predetermined forward gate bias. When the forward gate bias applied is below a certain level, the drain current will increase fundamentally exponentially with an increase of the drain voltage above some threshold voltage, whereas when the gate bias applied is above the certain value, the drain current will increase rapidly with a small increase in the drain voltage.

Abstract translation: 本发明人提出的具有非饱和特性的新型场效应晶体管即静电感应晶体管（SIT）被修改，以用作给定电路中任何常规双极晶体管的替代物。 也就是说，选择SIT的沟道区域的栅极到栅极间距和杂质浓度，以便在预定的正向栅极偏压下通过耗尽层夹持沟道。 当施加的正向栅极偏置低于一定电平时，漏极电流随着漏极电压增加到一定阈值电压的上升势头将呈指数增长，而当施加的栅极偏置高于某一值时，漏极电流将随着 漏极电压小幅增加。

公开(公告)号：US4572763A

公开(公告)日：1986-02-25

申请号：US513294

申请日：1983-07-13

Applicant: Jun-ichi Nishizawa

Inventor： Jun-ichi Nishizawa

IPC: C30B19/04 ,  C30B29/48 ,  H01L21/208 ,  H01L21/368 ,  C30B9/06

CPC classification number: C30B19/04 ,  C30B29/48 ,  Y10S117/90 ,  Y10S117/906

Abstract: In conducting a liquid phase epitaxial growth of a Zn crystal on a substrate wherein a batch of Se melt serving as a solvent is used and relying on a vapor pressure controlling technique and a temperature difference method, a Zn vapor pressure controlling region is disposed, via the Se melt, in a direction vertical to the surface of the substrate which is contained in the growth region, and a ZnSe source crystal is disposed in such a way that it is supplied into the Se melt in a lateral direction of this melt. Whereby, a ZnSe single crystal having a good crystal perfection, and a good linearity of the thickness of the grown crystal relative to time can be obtained.

Abstract translation: 在使用一批作为溶剂的Se熔体作为溶剂的基底上进行Zn晶体的液相外延生长，并依靠蒸气压控制技术和温差法，通过 Se沿垂直于包含在生长区域中的衬底的表面的方向熔化，并且ZnSe源晶体以这样的方式设置，使得它在该熔体的横向上被供应到Se熔体中。 由此，可以获得具有良好晶体完整性和生长晶体相对于时间的厚度线性良好的ZnSe单晶。

公开(公告)号：US4565156A

公开(公告)日：1986-01-21

申请号：US470541

申请日：1983-02-28

Applicant: Jun-ichi Nishizawa ,  Yasuo Okuno

Inventor： Jun-ichi Nishizawa ,  Yasuo Okuno

IPC: C30B19/08 ,  H01L21/208

CPC classification number: C30B19/08 ,  H01L21/02546 ,  H01L21/02625 ,  H01L21/02628

Abstract: A solution growth apparatus for conducting an epitaxial growth of a compound semiconductor crystal from solution by relying on the temperature difference technique at a constant growth temperature and on a mass production scale without deranging the control of the growth temperature applied externally of the growth apparatus and with the application of only a small heating power and only a small cooling power, by enhancing the thermal exchange efficiency through the provision of heating means, via an insulator, for the melt-containing reservoir provided on the growth boat housed within a quartz reactor and by the provision of cooling means at the bottom of the boat within the reactor.

Abstract translation: 一种溶液生长装置，用于通过在恒定生长温度和大规模生产规模下依靠温差技术从溶液中进行外延生长化学半导体晶体，而不会降低在生长装置外部施加的生长温度的控制，并且与 通过提供加热装置，通过绝缘体提供设置在容纳在石英反应器内的生长舟皿上的熔体容纳储存器以及通过设置在石英反应器内的生长舟上，通过提供热交换效率，仅通过提供热交换效率 在反应堆内的船底部设置冷却装置。