公开(公告)号：US5585654A

公开(公告)日：1996-12-17

申请号：US782789

申请日：1991-10-24

Applicant: Jun-ichi Nishizawa

Inventor： Jun-ichi Nishizawa

IPC: G11B3/12 ,  H01L29/10 ,  H01L29/772 ,  H01L29/808

CPC classification number: G11B3/128 ,  H01L29/1066 ,  H01L29/7722

Abstract: A field effect transistor has the property that the product of its series resistance and its true transconductance is less than one throughout the entire range of drain voltage in the operative state of the transistor, the series resistance being the sum of the resistance from source to channel and the resistance of this channel. In order to prevent an excessive increase in the active resistance of the channel, the channel is made to have an impurity concentration as low as less than 10.sup.15 atoms/cm.sup.3, preferably less than 10.sup.14 atoms/cm.sup.3, so that the depletion layers extending from the gates grow extensively to become contiguous in response to a small increase in the reverse gate voltage applied. As a result, the field effect transistor of this invention has an unsaturated drain current versus drain voltage characteristic.

Abstract translation: 场效应晶体管具有在晶体管的工作状态下，其串联电阻与其真正跨导的乘积在整个漏极电压范围内小于1的特性，串联电阻是源极与沟道之间的电阻之和 和这个渠道的阻力。 为了防止通道的有效电阻的过度增加，使沟道的杂质浓度低至1015原子/ cm3，优选小于1014原子/ cm3，从而从 栅极响应于施加的反向栅极电压的小的增加而广泛地生长以变得连续。 结果，本发明的场效晶体管具有不饱和漏极电流对漏极电压特性。

公开(公告)号：US5463977A

公开(公告)日：1995-11-07

申请号：US91747

申请日：1993-07-15

Applicant: Nobuaki Manada ,  Junji Ito ,  Toru Kurabayashi ,  Jun-ichi Nishizawa

Inventor： Nobuaki Manada ,  Junji Ito ,  Toru Kurabayashi ,  Jun-ichi Nishizawa

IPC: C30B25/14 ,  C30B25/16 ,  C30B29/42 ,  H01L21/205

CPC classification number: C23C16/45561 ,  C30B25/14 ,  C30B25/165

Abstract: In a method of and an apparatus for epitaxially growing a chemical-compound crystal, a plurality of raw-material gasses are alternately introduced into a closed chamber of a crystal growing device to grow the crystal placed within the closed chamber. At growing of the crystal, a light from a light source is emitted to a crystal growing film of the crystal. Intensity of a light reflected from the crystal growing film and received by a photo detector is measured. Charge amounts of the respective raw-material gasses are controlled by a control system on the basis of a change in the reflected-light intensity, thereby controlling a growing rate of the growing film.

Abstract translation: 在用于外延生长化合物晶体的方法和装置中，将多种原料气体交替地引入晶体生长装置的封闭室中以使放置在封闭室内的晶体生长。 在晶体生长时，来自光源的光被发射到晶体的晶体生长膜。 测量从晶体生长膜反射并由光电检测器接收的光的强度。 基于反射光强度的变化，通过控制系统控制各原料气体的电荷量，由此控制生长膜的生长速度。

公开(公告)号：US5384476A

公开(公告)日：1995-01-24

申请号：US62333

申请日：1987-06-09

Applicant: Jun-ichi Nishizawa ,  Tadahiro Ohmi

Inventor： Jun-ichi Nishizawa ,  Tadahiro Ohmi

IPC: H01L23/556 ,  H01L27/108 ,  H01L29/10 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L23/556 ,  H01L27/10808 ,  H01L29/105 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/7722 ,  H01L29/78 ,  H01L2924/0002

Abstract: A semiconductor device having a source region, a drain region and a channel region which are formed in a surface portion of a semiconductor substrate, and a gate formed with a material having a relatively high built-in voltage relative to the source region. This semiconductor device may further include, in the semiconductor substrate to extend along the channel region, a highly-doped region having a conductivity type opposite to that of the source region. This highly-closed region may have an impurity concentration gradient which is greater toward its portion facing the abovesaid surface of the substrate. These arrangements serve to prevent extinction of memory due to current leakage during absence of bias voltage which otherwise would develop in semiconductor devices having short-channel and thin gate oxide layer, and due to irradiation of alpha-particle onto the device.

Abstract translation: 具有形成在半导体基板的表面部分中的源极区域，漏极区域和沟道区域的半导体器件和形成有相对于源极区域具有相对较高内置电压的材料的栅极。 该半导体器件还可以在半导体衬底中沿沟道区域延伸具有与源极区域相反的导电类型的高掺杂区域。 这个高度封闭的区域可以具有对其面向衬底的上述表面的部分更大的杂质浓度梯度。 这些布置用于防止由于不存在偏置电压时的电流泄漏而导致的存储器的消光，否则将在具有短沟道和薄栅极氧化物层的半导体器件中以及由于α粒子照射到器件上而产生。

公开(公告)号：US5060029A

公开(公告)日：1991-10-22

申请号：US483740

申请日：1990-02-23

Applicant: Jun-ichi Nishizawa ,  Nobuo Takeda

Inventor： Jun-ichi Nishizawa ,  Nobuo Takeda

IPC: H01L21/28 ,  H01L21/335 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78

CPC classification number: H01L29/66416 ,  H01L21/28052 ,  H01L21/2815 ,  H01L29/4933 ,  H01L29/7722 ,  H01L29/7827

Abstract: This invention provides a step cut type insulated gate static induction tsistor having a first main electrode formed in one major surface of a semiconductor substrate, a second main electrode formed in a bottom portion of a U-shaped groove formed in one major surface of a semiconductor substrate, a control electrode formed on a side wall of the U-shaped groove and consisting of a thin insulating film and a polysilicon layer, and a low-resistance electrode of a refractory metal layer or a refractory metal silicide layer formed in at least part of the side wall of the polysilicon layer of the control electrode.

Abstract translation: 本发明提供了一种具有在半导体衬底的一个主表面上形成的第一主电极的切割型绝缘栅静电感应晶体管，形成在半导体的一个主表面上的U形槽的底部的第二主电极 基板，形成在U形槽的侧壁上并由薄绝缘膜和多晶硅层构成的控制电极以及难熔金属层或难熔金属硅化物层的低电阻电极，其形成在至少部分 的控制电极的多晶硅层的侧壁。

公开(公告)号：US5017991A

公开(公告)日：1991-05-21

申请号：US259438

申请日：1988-10-14

Applicant: Jun-ichi Nishizawa ,  Takashige Tamamushi ,  Ken-ichi Nonaka

Inventor： Jun-ichi Nishizawa ,  Takashige Tamamushi ,  Ken-ichi Nonaka

IPC: H01L29/10 ,  H01L29/739 ,  H01L29/74 ,  H01L29/744 ,  H01L31/10 ,  H01L31/111 ,  H02M1/08 ,  H03K17/78 ,  H03K17/79

CPC classification number: H01L29/102 ,  H01L29/1016 ,  H01L29/1066 ,  H01L29/7392 ,  H01L29/744 ,  H01L31/1113 ,  H03K17/79

Abstract: A thyristor device comprising an SI (Static induction) thyristor or beam base thyristor and an SIT (static induction transistor) or SIT-mode bipolar transistor connected to the gate of the thyristor in order to make it possible to turn-on and-off a direct current and voltage at a high speed with a light. In the thyristor part, the SIT gate structure or SIT-mode beam base structure exists in the first gate or base region or second gate or base region so that, at the time of the triggering operation, a very high switching efficiency will be obtained.

Abstract translation: 一种晶闸管器件，其包括连接到晶闸管的栅极的SI（静态感应）晶闸管或光束基极晶闸管和SIT（静态感应晶体管）或SIT模式双极晶体管，以便使得能够导通和断开 直流电和电压高速带光。 在晶闸管部分中，在第一栅极或基极区域或第二栅极或基极区域中存在SIT栅极结构或SIT模式波束基极结构，使得在触发操作时将获得非常高的开关效率。

公开(公告)号：US4994872A

公开(公告)日：1991-02-19

申请号：US225870

申请日：1988-07-29

Applicant: Jun-ichi Nishizawa ,  Tadahiro Ohmi

Inventor： Jun-ichi Nishizawa ,  Tadahiro Ohmi

IPC: H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423 ,  H01L29/772 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L27/0225 ,  H01L27/0883 ,  H01L27/092 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/7722 ,  H01L29/7801 ,  H01L29/4236 ,  H01L29/42368

Abstract: An insulated-gate static induction transistor is formed by establishing a potential barrier in a semiconductor region of one conductivity type between the source and the drain regions of the other conductivity type. The height of the potential barrier should be sensitive to the drain voltage as well as to the gate voltage. Therefore, the semiconductor region should have a low impurity concentration and short length. The potential barrier can be established by varying the field effect of the gate voltage in the semiconductor region and/or by the built-in potential between the source region and the semiconductor region.

公开(公告)号：US4985738A

公开(公告)日：1991-01-15

申请号：US939259

申请日：1986-12-05

Applicant: Jun-ichi Nishizawa ,  Tadahiro Ohmi

Inventor： Jun-ichi Nishizawa ,  Tadahiro Ohmi

IPC: H01L29/739

CPC classification number: H01L29/7392

Abstract: A semiconductor thyristor of the Static Induction type having a split-gate structure, e.g., driving gates and non-driving gates, for controlling cathode-anode current flow. The split-gate structure comprises a plurality of primary gates formed in recesses of the channel region which respond to an external control signal for providing primary current control, and a plurality of secondary non-driving gates which are influenced by electric fields in the channel region extant during thyristor operation for providing secondary current control. In operation, the driving and non-driving gates coact so that the non-driving gates, having an induced potential lower than the potential applied to the driving gates, absorb charge carriers injected in the channel during thyristor operation. The relative disposition of the non-driving gates and the anode, as well as the respective doping concentrations of the anode and channel regions, enable the non-driving gates to absorb a substantial portion of charge carriers injected from the anode into the channel during high-power operation. Fast turn-on and turn-off is achieved by exclusion of the non-driving gate capacitance in the driving gate circuit.

Abstract translation: 具有用于控制阴极 - 阳极电流的具有分离栅极结构（例如驱动栅极和非驱动栅极）的静态感应型的半导体晶闸管。 分离栅极结构包括形成在沟道区的凹部中的多个主栅极，其响应于用于提供初级电流控制的外部控制信号，以及受到沟道区域中的电场影响的多个次级非驱动栅极 在晶闸管操作期间提供二次电流控制。 在操作中，驱动和非驱动栅极共同作用，使得具有低于施加到驱动栅极的电位的感应电位的非驱动栅极在晶闸管操作期间吸收在沟道中注入的电荷载流子。 非驱动栅极和阳极的相对配置以及阳极和沟道区域的各自的掺杂浓度使得非驱动栅极能够在高的期间吸收从阳极注入到沟道中的大部分电荷载流子 电力操作。 通过排除驱动门电路中的非驱动栅极电容来实现快速导通和关断。

公开(公告)号：US4956599A

公开(公告)日：1990-09-11

申请号：US298900

申请日：1989-01-19

Applicant: Jun-ichi Nishizawa ,  Takashige Tamamushi ,  Koji Ishibashi ,  Kiyoshi Wagatsuma

Inventor： Jun-ichi Nishizawa ,  Takashige Tamamushi ,  Koji Ishibashi ,  Kiyoshi Wagatsuma

IPC: H02M5/257 ,  G05F1/10 ,  G05F1/455 ,  H02M1/08 ,  H03K17/725 ,  H03K17/79

CPC classification number: G05F1/455 ,  H03K17/725 ,  H03K17/79 ,  Y10S323/902

Abstract: A pair of static induction thyristors, which are coupled in parallel in the opposite bias directions between an AC power source and a load, is turned on by a light signal and is turned off by natural commutation, a light signal or an electric signal. The turn-off light signal is generated within a phase angle of 90.degree. in the time axis around the zero-cross point of the AC voltage from the AC power source.

公开(公告)号：US4939571A

公开(公告)日：1990-07-03

申请号：US082979

申请日：1987-08-04

Applicant: Jun-ichi Nishizawa ,  Tadahiro Ohmi

Inventor： Jun-ichi Nishizawa ,  Tadahiro Ohmi

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/772 ,  H01L29/78 ,  H01L29/80 ,  H03K19/091

CPC classification number: H03K19/0912 ,  H01L27/0883 ,  H01L27/092 ,  H01L29/7722 ,  H01L29/7835

Abstract: An insulated-gate type transistor having a semi-conductor body of a low impurity concentration, a heavily-doped source region of a conductivity type opposite to that of the semiconductor body for supplying charge carriers, a heavily-doped drain region for receiving the carriers supplied from the source region, both of which regions may be provided separately in a main surface of the body, a channel region located between the source and drain regions for the travel of these carriers, an insulated-gate structure inputted with a gate voltage for controlling the travel of those carriers, a semiconductor region formed in the neighborhood of the source region within the body and having a portion located below the source region and another portion extending beyond therefrom toward the drain region and serving to define the channel region and to increase the ratio of the amount of carriers reaching the drain region to the total amount of the carriers supplied from the source region. This transistor can be easily manufactured with a single substrate from that side of the main surface. This transistor is suitable for use in constructing integrated circuits and enables construction of complementary devices.

Abstract translation: 一种具有低杂质浓度的半导体体的绝缘栅型晶体管，具有与用于提供电荷载流子的半导体本体相反的导电类型的重掺杂源极区，用于接收载流子的重掺杂漏极区 从源极区域提供的两个区域可以分别设置在主体的主表面中，位于源极和漏极区之间的沟道区域用于这些载流子的行进，输入栅极电压的绝缘栅极结构 控制这些载体的行进，形成在体内源区域附近的半导体区域，并且具有位于源极区域下方的部分和从其延伸超过其的部分朝向漏极区域并且用于限定沟道区域并增加 到达漏极区的载流子的量与从源极区域供给的载流子的总量的比率。 该晶体管可以容易地从主表面的那一侧用单个衬底制造。 该晶体管适用于构建集成电路，并可构建互补器件。

公开(公告)号：US4783426A

公开(公告)日：1988-11-08

申请号：US124390

申请日：1987-11-19

Applicant: Jun-ichi Nishizawa

Inventor： Jun-ichi Nishizawa

IPC: C30B19/04 ,  H01L21/208 ,  H01L21/368 ,  H01L33/28

CPC classification number: H01L33/28 ,  C30B19/04 ,  C30B29/48 ,  H01L21/02409 ,  H01L21/02551 ,  H01L21/0256 ,  H01L21/02579 ,  H01L21/02581 ,  H01L21/02625 ,  H01L21/02628 ,  H01L33/0083

Abstract: A semiconductor device made of a II-VI compound semiconductor and having a p type semiconductor crystal. The p type semiconductor crystal is one obtained by growing the II-VI compound semiconductor crystal by relying on a liquid phase crystal growth process using a solvent comprised of one of Group II and Group VI elements constituting the Group II-VI compound semiconductor and having a higher vapor pressure over the other of these elements in an atmosphere comprised of the other of the elements having a lower vapor pressure under controlled vapor pressure of the atmosphere, and by doping into the solvent a p type impurity element selected from Group Ia and Ib elements in an amount of a range from 1.times.10.sup.-3 to 5.times.10.sup.-1 mol %. Thus, p type semiconductor crystals for use in semiconductor devices can be obtained easily from II-VI compound semiconductors. The present invention is especially effective in ZnSe crystals.

Abstract translation: 一种由II-VI化合物半导体制成且具有p型半导体晶体的半导体器件。 p型半导体晶体是通过使用由构成II-VI族化合物半导体的II族和VI族元素之一的溶剂依赖于液相晶体生长工艺来生长II-VI族化合物半导体晶体而得到的，具有 在气氛中受控蒸气压下具有较低蒸汽压的另一元素组成的气氛中，另外一种元素的蒸气压较高，并且掺杂到选自Ia和Ib族元素中的溶剂型p型杂质元素 其量为1×10 -3至5×10 -1 mol％。 因此，可以容易地从II-VI化合物半导体获得用于半导体器件的p型半导体晶体。 本发明在ZnSe晶体中特别有效。