公开(公告)号：US09159915B2

公开(公告)日：2015-10-13

申请号：US14132286

申请日：2013-12-18

申请人： Ovonyx, Inc.

发明人： Ilya V. Karpov ,  Sean Jong Lee ,  Yudong Kim ,  Greg Atwood

IPC分类号： H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC分类号： H01L45/141 ,  G11C13/0004 ,  H01L27/2427 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1683

摘要： An ovonic threshold switch may be formed of a continuous chalcogenide layer. That layer spans multiple cells, forming a phase change memory. In other words, the ovonic threshold switch may be formed of a chalcogenide layer which extends, uninterrupted, over numerous cells of a phase change memory.

摘要翻译： 可以由连续的硫族化物层形成一个超声阈值开关。 该层跨越多个单元，形成相变存储器。 换句话说，超声阈值开关可以由在相变存储器的多个单元上不间断地延伸的硫族化物层形成。

公开(公告)号：US09076521B2

公开(公告)日：2015-07-07

申请号：US13549436

申请日：2012-07-14

申请人： Ward Parkinson

发明人： Ward Parkinson

IPC分类号： G11C8/08 ,  G11C8/10 ,  G11C13/00

CPC分类号： G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76

摘要： A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be configured for operation with an external memory controller.

公开(公告)号：US09036409B2

公开(公告)日：2015-05-19

申请号：US14336600

申请日：2014-07-21

申请人： Ovonyx, Inc.

发明人： George A. Gordon ,  Semyon D. Savransky ,  Ward D. Parkinson ,  Sergey Kostylev ,  James Reed ,  Tyler A. Lowrey ,  Ilya V. Karpov ,  Gianpaolo Spadini

IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C8/10 ,  G11C11/56 ,  G11C16/34 ,  G11C29/04

CPC分类号： G11C13/0033 ,  G11C8/10 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/3431 ,  G11C29/04 ,  G11C2013/0052 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/76

摘要： Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb.

公开(公告)号：US08767440B2

公开(公告)日：2014-07-01

申请号：US13892499

申请日：2013-05-13

申请人： Ward Parkinson ,  Thomas Trent

发明人： Ward Parkinson ,  Thomas Trent

IPC分类号： G11C11/00

CPC分类号： G11C13/0033 ,  G11C11/22 ,  G11C13/0023

摘要： An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.

摘要翻译： 一种具有管理误差校正需求的短路缺陷的非易失性存储器阵列的寻址方案。 该方案通常避免在写入期间同时主动驱动所选单元的行线和列线。 相反，只有单行或列行在任何一个时间被主动驱动，所有其他的数组行都是浮动的。 此外，可以限制在取出期间从给定的行或列访问的存储器单元的数量。 该方案的优点包括防止短路引起阵列过剩的电流，并将由短路引起的读或写故障的频率限制在可管理的数量上。 在一个实施例中，该方案将对错误校正的需求保持在闪存控制器的纠错能力内。 示例性实施例包括相变存储器阵列。

公开(公告)号：US08565031B2

公开(公告)日：2013-10-22

申请号：US13561172

申请日：2012-07-30

申请人： Ferdinando Bedeschi ,  Claudio Resta

发明人： Ferdinando Bedeschi ,  Claudio Resta

IPC分类号： G11C7/06

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2211/5645 ,  G11C2213/79

摘要： A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.

摘要翻译： 一种用于读取适于存储逻辑值的至少一个存储单元的读取电路，所述至少一个存储单元包括：由相变材料制成的存储元件; 以及用于响应于所述存储单元的选择将所述存储元件耦合到所述读取电路的访问元件，所述读取电路包括：用于向所述至少一个存储器单元提供感测电流的感测电流供应装置; 以及至少一个读出放大器，用于基于在其上形成的电压来确定存储在存储器单元中的逻辑值，所述至少一个读出放大器包括用于限制存储器单元两端的电压的电压限制电路，用于保存所存储的逻辑值 其中所述电压限制电路包括用于吸收钳位电流的电流沉降片，其从所述感测电流中减去并且取决于所存储的逻辑值。

公开(公告)号：US08503219B2

公开(公告)日：2013-08-06

申请号：US13158531

申请日：2011-06-13

申请人： Ward Parkinson

发明人： Ward Parkinson

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0078 ,  G11C2013/0092

摘要： A programmable resistance memory employs a feedback control circuit to regulate the programming current supplied to a selected programmable resistance memory element. The programmable resistance memory may be a phase change memory. The feedback control circuit monitors and controls the characteristics of a current pulse employed to program a memory cell.

摘要翻译： 可编程电阻存储器采用反馈控制电路来调节提供给选定的可编程电阻存储元件的编程电流。 可编程电阻存储器可以是相变存储器。 反馈控制电路监视和控制用于编程存储器单元的电流脉冲的特性。

公开(公告)号：US08440535B2

公开(公告)日：2013-05-14

申请号：US13463072

申请日：2012-05-03

申请人： Charles H. Dennison

发明人： Charles H. Dennison

IPC分类号： H01L21/20 ,  H01L21/00 ,  H01L21/06

CPC分类号： H01L45/144 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/1675

摘要： A phase change memory may include an ovonic threshold switch formed over an cyanic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.

摘要翻译： 相变存储器可以包括在氰色存储器上形成的超声阈值开关。 在一个实施例中，开关包括与下面的电极重叠的硫族化物层。 然后，由于蚀刻硫族化物层而导致的边缘损坏可以被隔离以减少漏电流。

公开(公告)号：US08363446B2

公开(公告)日：2013-01-29

申请号：US12578638

申请日：2009-10-14

申请人： Wolodymyr Czubatyj ,  Tyler Lowrey ,  Charles Dennison ,  Carl Schell

发明人： Wolodymyr Czubatyj ,  Tyler Lowrey ,  Charles Dennison ,  Carl Schell

IPC分类号： G11C11/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

摘要： A method of programming an electrical variable resistance memory device. When applied to variable resistance memory devices that incorporate a phase-change material as the active material, the method utilizes a plurality of crystalline programming states. The crystalline programming states are distinguishable on the basis of resistance, where the resistance values of the different states are stable with time and exhibit little or no drift. As a result, the programming scheme is particularly suited to multilevel memory applications. The crystalline programming states may be achieved by stabilizing crystalline phases that adopt different crystallographic structures or by stabilizing crystalline phases that include mixtures of two or more distinct crystallographic structures that vary in the relative proportions of the different crystallographic structures. The programming scheme incorporates at least two crystalline programming states and further includes at least a third programming state that may be a crystalline, amorphous or mixed crystalline-amorphous state.

摘要翻译： 一种编程电可变电阻存储器件的方法。 当应用于包含相变材料作为活性材料的可变电阻存储器件时，该方法利用多个晶体编程状态。 结晶编程状态可以根据电阻进行区分，其中不同状态的电阻值随时间稳定并且表现出很小的或没有漂移。 因此，编程方案特别适用于多层存储器应用。 晶体编程状态可以通过稳定采用不同晶体结构的结晶相或通过稳定结晶相来实现，所述结晶相包括两种或更多种不同结晶学结构的混合物，其在不同结晶学结构的相对比例中变化。 编程方案包含至少两个晶体编程状态，并且还包括至少第三编程状态，其可以是晶体，无定形或混合晶体 - 非晶状态。

公开(公告)号：US08351250B2

公开(公告)日：2013-01-08

申请号：US12229997

申请日：2008-08-28

申请人： Tyler Lowrey

发明人： Tyler Lowrey

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C2213/72

摘要： A memory includes a programmable resistance array and unipolar MOS peripheral circuitry. The peripheral circuitry includes address decoding circuitry. Because unipolar MOS circuitry is employed, the number of mask steps and, concomitantly, the cost of the programmable resistance memory may be minimized.

摘要翻译： 存储器包括可编程电阻阵列和单极MOS外围电路。 外围电路包括地址解码电路。 因为采用单极MOS电路，所以可以将屏蔽步骤的数量以及伴随的可编程电阻存储器的成本最小化。

公开(公告)号：US08344350B2

公开(公告)日：2013-01-01

申请号：US13093109

申请日：2011-04-25

申请人： Wolodymyr Czubatyj ,  Tyler Lowrey

发明人： Wolodymyr Czubatyj ,  Tyler Lowrey

IPC分类号： H01L21/06 ,  H01L45/00

CPC分类号： H01L45/1683 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/126

摘要： A programmable resistance memory combines multiple cells into a block that includes one or more shared electrodes. The shared electrode configuration provides additional thermal isolation for the active region of each memory cell, thereby reducing the current required to program each memory cell.

摘要翻译： 可编程电阻存储器将多个单元组合成包括一个或多个共享电极的块。 共享电极配置为每个存储单元的有源区域提供额外的热隔离，从而减少编程每个存储单元所需的电流。