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公开(公告)号：US20160162213A1
公开(公告)日：2016-06-09
申请号：US15012478
申请日：2016-02-01
CPC分类号： G06F3/0622 , G06F3/0643 , G06F3/0679 , G11C13/0004 , G11C13/004 , G11C13/0059 , G11C13/0069 , G11C13/0097 , G11C13/02 , H01L45/04 , H01L45/06
摘要： Methods of operating memory arrays are described. In various embodiments, a method includes determining a pattern to be written to a memory array, the pattern comprising both data bits having sensitive information to be stored and data bits having a state that is unimportant to the sensitive information to be stored, and writing the pattern to the memory array. Other methods of operation are also described.
摘要翻译： 描述操作存储器阵列的方法。 在各种实施例中，一种方法包括确定要写入存储器阵列的模式，该模式包括具有要存储的敏感信息的数据位和具有与要存储的敏感信息不重要的状态的数据位，以及写入 模式到内存数组。 还描述了其他操作方法。
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2.发明申请公开(公告)号：US20120307553A1
公开(公告)日：2012-12-06
申请号：US13561172
申请日：2012-07-30
申请人： Ferdinando Bedeschi , Claudio Resta
发明人： Ferdinando Bedeschi , Claudio Resta
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C2013/0054 , G11C2211/5645 , G11C2213/79
摘要： A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.
摘要翻译： 一种用于读取适于存储逻辑值的至少一个存储单元的读取电路，所述至少一个存储单元包括：由相变材料制成的存储元件; 以及用于响应于所述存储单元的选择将所述存储元件耦合到所述读取电路的访问元件，所述读取电路包括：用于向所述至少一个存储器单元提供感测电流的感测电流供应装置; 以及至少一个读出放大器，用于基于在其上形成的电压来确定存储在存储器单元中的逻辑值，所述至少一个读出放大器包括用于限制存储器单元两端的电压的电压限制电路，用于保存所存储的逻辑值 其中所述电压限制电路包括用于吸收钳位电流的电流沉降片，其从所述感测电流中减去并且取决于所存储的逻辑值。
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3.发明授权Phase-change memory device with discharge of leakage currents in deselected bitlines and method for discharging leakage currents in deselected bitlines of a phase-change memory device 有权在取消选择的位线中泄漏电流放电的相变存储器件和用于在相变存储器件的未选定位线中泄漏泄漏电流的方法公开(公告)号：US08223535B2
公开(公告)日：2012-07-17
申请号：US12560235
申请日：2009-09-15
申请人： Ferdinando Bedeschi , Claudio Resta
发明人： Ferdinando Bedeschi , Claudio Resta
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0026 , G11C13/003 , G11C13/0038 , G11C2213/79
摘要： A phase change memory device includes a bitline biasing unit; and a bitline selection unit connecting a selected bitline to the bitline biasing unit and disconnecting deselected bitlines from the bitline biasing unit in an operative condition. A bitline discharge unit is connected to the bitlines to discharge leakage currents in the bitlines. The bitline discharge unit has a voltage regulation unit and a plurality of bitline discharge switches coupled between the voltage regulation unit and a respective bitline. The bitline discharge switches are controlled to connect the deselected bitlines to the voltage regulation unit and to disconnect the selected bitline from the voltage regulation unit. The voltage regulation unit comprises a PMOS transistor coupled between a regulated voltage bus and a reference potential line. The regulated voltage bus is connected to the bitline discharge switches and the control terminal of the PMOS transistor is biased to a constant voltage.
摘要翻译： 相变存储器件包括位线偏置单元; 以及位线选择单元，其将所选择的位线连接到所述位线偏置单元，并且在操作状态下将所选择的位线与所述位线偏置单元断开。 位线放电单元连接到位线以排除位线中的泄漏电流。 位线放电单元具有电压调节单元和耦合在电压调节单元和相应位线之间的多个位线放电开关。 控制位线放电开关将取消选择的位线连接到电压调节单元，并将选定的位线与电压调节单元断开。 电压调节单元包括耦合在调节电压总线和参考电位线之间的PMOS晶体管。 调节电压总线连接到位线放电开关，PMOS晶体管的控制端被偏置为恒定电压。
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公开(公告)号：US20110176358A1
公开(公告)日：2011-07-21
申请号：US13072911
申请日：2011-03-28
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C2013/0045 , G11C2013/0054 , G11C2013/0066 , G11C2213/75 , G11C2213/76
摘要： A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element.
摘要翻译： 可以使用高达阈值相变存储器元件的读取电流来读取元件而不对存储元件进行阈值化。 在某些情况下，较高的电流可能会改善性能。 由于读取元素并且在触发存储器元件之前停止了当前存储器元件，因此存储器元件不会被阈值。
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5.发明授权Method for low-stress multilevel reading of phase change memory cells and multilevel phase change memory 有权相变存储器单元和多电平相变存储器的低应力多电平读取方法公开(公告)号：US07885101B2
公开(公告)日：2011-02-08
申请号：US12345398
申请日：2008-12-29
IPC分类号： G11C11/00
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0076
摘要： According to a method for multilevel reading of a phase change memory cell a bit line (9) and a PCM cell (2) are first selected and a first bias voltage (VBL, V00) is applied to the selected bit line (9). A first read current (IRD00), that flows through the selected bit line (9) in response to the first bias voltage (VBL, V00), is compared with a first reference current (I00). The first reference current (I00) is such that the first read current (IRD00) is lower than the first reference current (I00), when the selected PCM cell (2) is in a reset state, and is otherwise greater. It is then determined whether the selected PCM cell (2) is in the reset state, based on comparing the first read current (IRD00) with the first reference current (I00). A second bias voltage (VBL, V01), greater than the first bias voltage (VBL, V00), is applied to the selected bit line (9) if the selected PCM cell (2) is not in the reset state.
摘要翻译： 根据用于相变存储单元的多电平读取的方法，首先选择位线（9）和PCM单元（2），并且将第一偏置电压（VBL，V00）施加到所选择的位线（9）。 将响应于第一偏置电压（VBL，V00）流过所选位线（9）的第一读取电流（IRD00）与第一参考电流（I00）进行比较。 当选择的PCM单元（2）处于复位状态时，第一参考电流（I00）使得第一读取电流（IRD00）低于第一参考电流（I00），否则更大。 基于将第一读取电流（IRD00）与第一参考电流（I00）进行比较，确定所选择的PCM单元（2）是否处于复位状态。 如果所选PCM单元（2）不处于复位状态，则将大于第一偏置电压（VBL，V00）的第二偏置电压（VBL，V01）施加到所选位线（9）。
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公开(公告)号：US07787291B2
公开(公告)日：2010-08-31
申请号：US11904306
申请日：2007-09-26
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/0078 , G11C2013/0092
摘要： Multilevel phase change memory cells may be programmed forming amorphous regions of amorphous phase change material in a storage region of the phase change memory cell. Crystalline paths of crystalline phase change material are formed through the amorphous regions of amorphous phase change material. Lengths of the crystalline paths are controlled so that at least a first crystalline path has a first length in a first programming state and a second crystalline path has a second length, different from the first length, in a second programming state.
摘要翻译： 多级相变存储器单元可以被编程为在相变存储单元的存储区域中形成无定形相变材料的非晶区域。 通过非晶相变材料的非晶区形成结晶相变材料的结晶路径。 控制晶体路径的长度，使得至少第一晶体路径在第二编程状态下具有处于第一编程状态的第一长度，并且第二晶体路径具有与第一长度不同的第二长度。
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7.发明申请公开(公告)号：US20100141335A1
公开(公告)日：2010-06-10
申请号：US12570770
申请日：2009-09-30
申请人： Ferdinando Bedeschi , Claudio Resta
发明人： Ferdinando Bedeschi , Claudio Resta
IPC分类号： G05F3/02
CPC分类号： G05F3/26
摘要： A current mirror circuit is provided with a first current mirror including a first and a second mirror transistors sharing a common control terminal; the first mirror transistor has a conduction terminal for receiving, during a first operating condition, a first reference current, and the second mirror transistor has a respective conduction terminal for providing, during the first operating condition, a mirrored current based on the first reference current. The current mirror circuit is provided with a switching stage operable to connect the control terminal to the conduction terminal of the first mirror transistor during the first operating condition, and to disconnect the control terminal from the same conduction terminal of the first mirror transistor, and either letting it substantially floating or connecting it to a reference voltage, during a second operating condition, in particular a condition of stand-by.
摘要翻译： 电流镜电路设置有第一电流镜，其包括共享公共控制端的第一和第二镜晶体管; 第一反射镜晶体管具有用于在第一操作条件期间接收第一参考电流的导电端子，并且第二反射镜晶体管具有相应的导通端子，用于在第一操作条件期间提供基于第一参考电流的镜像电流 。 电流镜电路设置有开关级，可操作以在第一操作状态期间将控制端连接到第一镜晶体管的导通端，并且将控制端与第一镜晶体管的相同导通端断开， 使其在第二操作条件期间基本上浮动或将其连接到参考电压，特别是待机条件。
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8.发明授权公开(公告)号：US07414902B2
公开(公告)日：2008-08-19
申请号：US11415879
申请日：2006-05-01
申请人： Claudio Resta , Ferdinando Bedeschi
发明人： Claudio Resta , Ferdinando Bedeschi
IPC分类号： G11C29/00
CPC分类号： G11C13/0004 , G11C11/22 , G11C11/2275 , G11C13/0033 , G11C13/0069 , G11C16/3431 , G11C2013/0083
摘要： A semiconductor memory device, including a plurality of programmable memory cells each one adapted to be brought into one among at least a first status and a second status, said plurality of memory cells including memory cells intended to store data, and means for accessing the memory cells for reading/modifying their status. At least one memory cell in said plurality is used as detector memory cell, and control means operatively associated with the at least one detector memory cell are provided, said control means being adapted to establishing a potential loss of the data stored in the memory cells of said plurality based on a detected first status of the at least one detector memory cell.
摘要翻译： 一种半导体存储器件，包括多个可编程存储器单元，每个可编程存储器单元适于在至少第一状态和第二状态之间变为一个，所述多个存储器单元包括用于存储数据的存储单元，以及用于存取存储器的装置 用于阅读/修改其状态的单元格。 所述多个中的至少一个存储单元被用作检测器存储器单元，并且提供与所述至少一个检测器存储单元可操作地相关联的控制装置，所述控制装置适于建立存储在存储单元中的数据的潜在损耗 所述多个基于所述至少一个检测器存储单元的检测到的第一状态。
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公开(公告)号：US07149132B2
公开(公告)日：2006-12-12
申请号：US10948885
申请日：2004-09-24
申请人： Ferdinando Bedeschi , Claudio Resta
发明人： Ferdinando Bedeschi , Claudio Resta
IPC分类号： G11C16/30
CPC分类号： G11C8/08
摘要： A biasing circuit for use in a non-volatile memory device is coupled to the row decoder and to the column decoder to supply a first and at least a second biasing voltage for the word and bit lines, and includes a first voltage booster having a first input coupled to receive a supply voltage, a second input coupled to receive a reference voltage, and an output coupled to one of the row decoder and the column decoder to supply the first biasing voltage. A second voltage booster has a first input coupled to receive the supply voltage, a second input coupled to the output of the first voltage booster to receive the first biasing voltage, and an output coupled to the other of the row decoder and the column decoder to supply the second biasing voltage.
摘要翻译： 用于非易失性存储器件的偏置电路耦合到行解码器和列解码器，以为字和位线提供第一和至少第二偏置电压，并且包括第一电压升压器，其具有第一 耦合以接收电源电压的输入，耦合以接收参考电压的第二输入，以及耦合到行解码器和列解码器之一以提供第一偏置电压的输出。 第二电压升压器具有耦合以接收电源电压的第一输入，耦合到第一电压升压器的输出以接收第一偏置电压的第二输入，以及耦合到行解码器和列解码器中的另一个的输出 提供第二偏置电压。
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10.发明授权Circuit and method for temperature tracing of devices including an element of chalcogenic material, in particular phase change memory devices 有权用于包括硫属元素元素的装置的温度追踪的电路和方法，特别是相变存储器件公开(公告)号：US07020014B2
公开(公告)日：2006-03-28
申请号：US10715883
申请日：2003-11-18
申请人： Osama Khouri , Ferdinando Bedeschi , Claudio Resta
发明人： Osama Khouri , Ferdinando Bedeschi , Claudio Resta
IPC分类号： G11C11/00
CPC分类号： G11C7/04 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0078 , G11C2013/009 , G11C2029/5002 , G11C2213/79
摘要： A phase change memory includes a temperature sensor having a resistance variable with temperature with the same law as a phase-change storage element. The temperature sensor is formed by a resistor of chalcogenic material furnishing an electrical quantity that reproduces the relationship between the resistance of a phase change memory cell and temperature; the electrical quantity is processed so as to generate reference quantities as necessary for writing and reading the memory cells. The chalcogenic resistor has the same structure as a memory cell and is programmed with precision, preferably in the reset state.
摘要翻译： 相变存储器包括具有与相变存储元件相同定律的具有温度的电阻变化的温度传感器。 该温度传感器是由一个硫化物材料的电阻器形成的，它提供一个再现相变存储器单元电阻和温度之间的关系的电量; 对电量进行处理，以便产生写入和读取存储单元所需的参考量。 硫属电阻器具有与存储器单元相同的结构，并且精确地编程，优选地处于复位状态。
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