TRANSMISSION/RECEPTION OF A PARTIAL SC-FDM SYMBOL

    公开(公告)号:US20170214559A1

    公开(公告)日:2017-07-27

    申请号:US15114160

    申请日:2014-01-29

    IPC分类号: H04L27/12 H04L25/03 H04L29/06

    摘要: A method is disclosed for signal processing in a radio system. The method comprises generating (801), in an apparatus (602), a single carrier frequency division multiplexing SC-FDM signal having a shorter duration than a time symbol duration defined by a radio standard applied in the radio system. The signal is transmitted (802) from the communications apparatus (602). The method comprises receiving (803) said signal from the communications apparatus (602), wherein orthogonality of frequency subcarriers is maintained at a receiver (601) of the signal.

    METHOD AND MEASURING DEVICE FOR INTERMODULATION MEASUREMENT

    公开(公告)号:US20170126337A1

    公开(公告)日:2017-05-04

    申请号:US15310867

    申请日:2014-09-19

    摘要: A method for intermodulation measurement for locating points in a signal transmission path for a high-frequency signal that are faulty with regard to HF transmission properties of the signal transmission path, by generating a first HF signal uTest, having a carrier frequency f1 and a digital signal uCode modulated thereon; generating a second HF signal u2 having a frequency f2; introducing the first HF signal uTest and the second HF signal u2 into the signal transmission path at a predetermined introduction point; receiving an intermodulation product, which is generated in the signal transmission path from the first HF signal and the second HF signal at at least one faulty point, as an intermodulation product signal uRX; recovering a digital signal udemod from uRX; and determining a time shift tx between the digital signal uCode and the recovered digital signal udemod. The invention further relates to a measuring device for performing this method.

    OPEN-LOOP QUADRATURE CLOCK CORRECTOR AND GENERATOR
    90.
    发明申请
    OPEN-LOOP QUADRATURE CLOCK CORRECTOR AND GENERATOR 有权
    OPEN-LOOP QUADRATURE时钟校正器和发生器

    公开(公告)号:US20170063353A1

    公开(公告)日:2017-03-02

    申请号:US14841874

    申请日:2015-09-01

    摘要: Embodiments described herein include a quadrature phase corrector (QPC) which includes multiple differential amplifies for correcting the phase of one or more clock signals. In one embodiment, the differential amplifiers are arranged in an input stage, cross-coupled stage, and ring stage. The input stage receives and buffers the input clock signal (or signals). The cross-coupled stage includes one or more latches that force one clock signal high and another low which causes the QPC to oscillate. The ring stage outputs four clock signals with adjusted phases relative to the input clock signals. In one example, the ring stage outputs a quadrature clock signal that includes four clock signals phase shifted by 90 degrees.

    摘要翻译: 本文描述的实施例包括正交相位校正器(QPC),其包括用于校正一个或多个时钟信号的相位的多个差分放大器。 在一个实施例中,差分放大器被布置在输入级,交叉耦合级和环形级中。 输入级接收并缓冲输入时钟信号(或信号)。 交叉耦合级包括一个或多个锁存器,其强制一个时钟信号为高,另一个低电平使QPC振荡。 环形电平输出四个时钟信号,相对于输入时钟信号调节相位。 在一个示例中,环形电平输出包括相移90度的四个时钟信号的正交时钟信号。