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    GROUP III-V COMPOUND SEMICONDUCTOR PHOTO DETECTOR, METHOD OF FABRICATING GROUP III-V COMPOUND SEMICONDUCTOR PHOTO DETECTOR, PHOTO DETECTOR, AND EPITAXIAL WAFER
    81.
    发明申请
    GROUP III-V COMPOUND SEMICONDUCTOR PHOTO DETECTOR, METHOD OF FABRICATING GROUP III-V COMPOUND SEMICONDUCTOR PHOTO DETECTOR, PHOTO DETECTOR, AND EPITAXIAL WAFER 审中-公开
    III-V族化合物半导体照相检测器，III-V族化合物半导体照相检测器，照相检测器和外延波形的方法

    公开(公告)号：US20150001466A1

    公开(公告)日：2015-01-01

    申请号：US14490128

    申请日：2014-09-18

    Applicant: Sumitomo Electric Industries, Ltd.

    Inventor： Katsushi Akita ,  Takashi Ishizuka ,  Kei Fujii ,  Youichi Nagai

    IPC: H01L31/0352 ,  H01L31/0304

    CPC classification number: H01L31/035209 ,  H01L21/02392 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02507 ,  H01L21/02546 ,  H01L31/03042 ,  H01L31/03046 ,  H01L31/035236 ,  H01L31/109 ,  H01L31/184 ,  Y02E10/544 ,  Y02P70/521

    Abstract: An object of the present invention is to provide a group III-V compound semiconductor photo detector comprising an absorption layer having a group III-V compound semiconductor layer containing Sb as a group V constituent element, and an n-type InP window layer, resulting in reduced dark current. The InP layer 23 grown on the absorption layer 23 contains antimony as impurity, due to the memory effect with antimony which is supplied during the growth of a GaAsSb layer of the absorption layer 21. In the group III-V compound semiconductor photo detector 11, the InP layer 23 contains antimony as impurity and is doped with silicon as n-type dopant. Although antimony impurities in the InP layer 23 generate holes, the silicon contained in the InP layer 23 compensates for the generated carriers. As a result, the second portion 23d of the InP layer 23 has sufficient n-type conductivity.

    Abstract translation: 本发明的目的是提供一种III-V族化合物半导体光电检测器，其包括具有含有Sb作为V族构成元素的III-V族化合物半导体层和n型InP窗口层的吸收层，得到 在减少的暗电流。 由于在吸收层21的GaAsSb层生长期间提供的锑的记忆效应，在吸收层23上生长的InP层23含有锑作为杂质。在III-V族化合物半导体光电检测器11中， InP层23含有锑作为杂质，并掺杂有硅作为n型掺杂剂。 虽然InP层23中的锑杂质产生空穴，但是包含在InP层23中的硅补偿所生成的载流子。 结果，InP层23的第二部分23d具有足够的n型导电性。

    Silicon carbide epitaxial wafer and semiconductor device
    82.
    发明授权
    Silicon carbide epitaxial wafer and semiconductor device 有权
    碳化硅外延片和半导体器件

    公开(公告)号：US08916880B2

    公开(公告)日：2014-12-23

    申请号：US13808382

    申请日：2011-07-14

    Applicant: Kenichi Ohtsuka ,  Nobuyuki Tomita ,  Tomoaki Furusho

    Inventor： Kenichi Ohtsuka ,  Nobuyuki Tomita ,  Tomoaki Furusho

    IPC: H01L29/16 ,  H01L21/02 ,  H01L29/66

    CPC classification number: H01L29/1608 ,  H01L21/02447 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/02573 ,  H01L21/0262 ,  H01L29/6606 ,  H01L29/66068

    Abstract: A semiconductor device that can suppress deterioration in crystal quality caused by a lattice mismatch between a substrate and an epitaxial layer and that also can ensure a voltage sustaining performance, and a wafer for forming the semiconductor device. An epitaxial wafer of silicon carbide (SiC), which is used for manufacturing a semiconductor device, includes a low resistance substrate and an epitaxial layer provided thereon. The epitaxial layer is doped with the same dopant as a dopant doped into the substrate, and has a laminated structure including a low concentration layer and an ultrathin high concentration layer. A doping concentration in the low concentration layer is lower than that in the silicon carbide substrate. A doping concentration in the ultrathin high concentration layer is equal to that in the silicon carbide substrate.

    Abstract translation: 能够抑制由基板与外延层之间的晶格失配引起的晶体质量下降的半导体器件，并且还可以确保电压维持性能，以及用于形成半导体器件的晶片。 用于制造半导体器件的碳化硅（SiC）的外延晶片包括低电阻基板和设置在其上的外延层。 外延层掺杂有与掺杂到衬底中的掺杂剂相同的掺杂剂，并且具有包括低浓度层和超薄高浓度层的层压结构。 低浓度层中的掺杂浓度低于碳化硅衬底中的掺杂浓度。 超薄高浓度层中的掺杂浓度等于碳化硅衬底中的掺杂浓度。

    TENSILE STRESSED DOPED AMORPHOUS SILICON
    83.
    发明申请
    TENSILE STRESSED DOPED AMORPHOUS SILICON 有权
    拉伸应力非晶硅

    公开(公告)号：US20140357064A1

    公开(公告)日：2014-12-04

    申请号：US13907742

    申请日：2013-05-31

    Applicant: Novellus Systems, Inc.

    Inventor： Keith Fox ,  Dong Niu ,  Joseph L. Womack

    IPC: H01L21/02

    CPC classification number: H01L21/02694 ,  H01L21/02123 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02507 ,  H01L21/02532 ,  H01L27/11582

    Abstract: The method and apparatus disclosed herein relate to preparing a stack structure for an electronic device on a semiconductor substrate. A particularly beneficial application of the method is in reduction of internal stress in a stack containing multiple layers of silicon. Typically, though not necessarily, the internal stress is a compressive stress, which often manifests as wafer bow. In some embodiments, the method reduces the internal stress of a work piece by depositing phosphorus doped silicon layers having low internal compressive stress or even tensile stress. The method and apparatus disclosed herein can be used to reduce compressive bow in stacks containing silicon.

    Abstract translation: 本文公开的方法和装置涉及制备半导体衬底上的电子器件的堆叠结构。 该方法的特别有益的应用是减少包含多层硅的堆叠中的内部应力。 通常，尽管不一定，内部应力是压缩应力，其通常表现为晶片弓。 在一些实施例中，该方法通过沉积具有低内部压缩应力或甚至拉伸应力的磷掺杂硅层来降低工件的内部应力。 本文公开的方法和装置可以用于减少包含硅的堆叠中的压缩弓。

    NITRIDE SEMICONDUCTOR SUBSTRATE
    86.
    发明申请
    NITRIDE SEMICONDUCTOR SUBSTRATE 有权
    氮化物半导体基板

    公开(公告)号：US20140339679A1

    公开(公告)日：2014-11-20

    申请号：US14271521

    申请日：2014-05-07

    Applicant: Covalent Materials Corporation

    Inventor： Jun KOMIYAMA ,  Akira YOSHIDA ,  Hiroshi OISHI

    IPC: H01L29/20

    CPC classification number: H01L29/2003 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1075 ,  H01L29/7786

    Abstract: A nitride semiconductor substrate suitable for a high withstand voltage power device is provided in which current collapse is controlled, while reducing leakage current. In a nitride semiconductor substrate, wherein a buffer layer, an active layer, and an electron supply layer, each comprising a group 13 nitride, are stacked one by one on a silicon single crystal substrate, the buffer layer has a structure where a multilayer stack in which a pair of nitride layers having different concentrations of Al or Ga are repeatedly deposited a plurality of times on an initial layer of AlxGa1-xN (0≦x≦1) is stacked, and includes a doping layer whose carbon concentration is 1×1018 to 1×1021 cm−3 and whose Si concentration is 1×1017 to 1×1020 cm−3, a thickness of the doping layer is 15% or more of the total thickness of the buffer layer.

    Abstract translation: 提供适用于高耐压功率器件的氮化物半导体衬底，其中电流崩溃被控制，同时减少漏电流。 在氮化硅半导体衬底中，其中每个包含13族氮化物的缓冲层，有源层和电子供给层在硅单晶衬底上一个一个堆叠，缓冲层具有多层叠层 其中在Al x Ga 1-x N（0＆amp; nlE; x＆lt; 1 | 1）的初始层上重复沉积多个Al或Ga的不同浓度的一对氮化物层，并且包括碳浓度为1× 1018〜1×1021cm-3，Si的浓度为1×1017〜1×1020cm-3，掺杂层的厚度为缓冲层的总厚度的15％以上。

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