Tensile stressed doped amorphous silicon
    1.
    发明授权
    Tensile stressed doped amorphous silicon 有权
    拉伸应力掺杂非晶硅

    公开(公告)号:US08895415B1

    公开(公告)日:2014-11-25

    申请号:US13907742

    申请日:2013-05-31

    IPC分类号: H01L21/205 H01L21/02

    摘要: The method and apparatus disclosed herein relate to preparing a stack structure for an electronic device on a semiconductor substrate. A particularly beneficial application of the method is in reduction of internal stress in a stack containing multiple layers of silicon. Typically, though not necessarily, the internal stress is a compressive stress, which often manifests as wafer bow. In some embodiments, the method reduces the internal stress of a work piece by depositing phosphorus doped silicon layers having low internal compressive stress or even tensile stress. The method and apparatus disclosed herein can be used to reduce compressive bow in stacks containing silicon.

    摘要翻译: 本文公开的方法和装置涉及制备半导体衬底上的电子器件的堆叠结构。 该方法的特别有益的应用是减少包含多层硅的堆叠中的内部应力。 通常,尽管不一定,内部应力是压缩应力,其通常表现为晶片弓。 在一些实施例中,该方法通过沉积具有低内部压缩应力或甚至拉伸应力的磷掺杂硅层来降低工件的内部应力。 本文公开的方法和装置可以用于减少包含硅的堆叠中的压缩弓。

    PECVD DEPOSITION OF SMOOTH SILICON FILMS
    2.
    发明申请
    PECVD DEPOSITION OF SMOOTH SILICON FILMS 审中-公开
    PECVD沉积硅薄膜

    公开(公告)号:US20150325435A1

    公开(公告)日:2015-11-12

    申请号:US14802766

    申请日:2015-07-17

    摘要: Smooth silicon films having low compressive stress and smooth tensile silicon films are deposited by plasma enhanced chemical vapor deposition (PECVD) using a process gas comprising a silicon-containing precursor (e.g., silane), argon, and a second gas, such as helium, hydrogen, or a combination of helium and hydrogen. Doped smooth silicon films and smooth silicon germanium films can be obtained by adding a source of dopant or a germanium-containing precursor to the process gas. In some embodiments dual frequency plasma comprising high frequency (HF) and low frequency (LF) components is used during deposition, resulting in improved film roughness. The films are characterized by roughness (Ra) of less than about 7 Å, such as less than about 5 Å as measured by atomic force microscopy (AFM), and a compressive stress of less than about 500 MPa in absolute value. In some embodiments smooth tensile silicon films are obtained.

    摘要翻译: 通过等离子体增强化学气相沉积(PECVD),使用包含含硅前体(例如硅烷),氩气和第二气体如氦气的工艺气体沉积具有低压缩应力和平滑拉伸硅膜的平滑硅膜, 氢或氦和氢的组合。 通过向工艺气体中加入掺杂剂源或含锗前体源可以获得掺杂的平滑硅膜和平滑硅锗膜。 在一些实施例中,在沉积期间使用包括高频(HF)和低频(LF)分量的双频等离子体等离子体,导致改善的膜粗糙度。 膜的特征在于通过原子力显微镜(AFM)测量的小于约等于小于约5埃的粗糙度(Ra)和绝对值小于约500MPa的压缩应力。 在一些实施方案中,获得平滑的拉伸硅膜。

    Post-deposition soft annealing
    3.
    发明授权
    Post-deposition soft annealing 有权
    后沉积软退火

    公开(公告)号:US09165788B2

    公开(公告)日:2015-10-20

    申请号:US13857566

    申请日:2013-04-05

    摘要: The methods and apparatus disclosed herein concern a process that may be referred to as a “soft anneal.” A soft anneal provides various benefits. Fundamentally, it reduces the internal stress in one or more silicon layers of a work piece. Typically, though not necessarily, the internal stress is a compressive stress. A particularly beneficial application of a soft anneal is in reduction of internal stress in a stack containing two or more layers of silicon. Often, the internal stress of a layer or group of layers in a stack is manifest as wafer bow. The soft anneal process can be used to reduce compressive bow in stacks containing silicon. The soft anneal process may be performed without causing the silicon in the stack to become activated.

    摘要翻译: 本文公开的方法和装置涉及可被称为“软退火”的方法。软退火提供了各种益处。 从根本上说,它降低了工件的一个或多个硅层的内应力。 通常,尽管不一定,内应力是压应力。 软退火的特别有益的应用是在包含两层或更多层硅的堆叠中减少内部应力。 通常,堆叠中的一层或多层层的内应力显示为晶片弓。 软退火工艺可用于减少含硅堆叠中的压缩弓。 可以执行软退火工艺,而不会使堆叠中的硅变得活化。

    TENSILE STRESSED DOPED AMORPHOUS SILICON
    6.
    发明申请
    TENSILE STRESSED DOPED AMORPHOUS SILICON 有权
    拉伸应力非晶硅

    公开(公告)号:US20140357064A1

    公开(公告)日:2014-12-04

    申请号:US13907742

    申请日:2013-05-31

    IPC分类号: H01L21/02

    摘要: The method and apparatus disclosed herein relate to preparing a stack structure for an electronic device on a semiconductor substrate. A particularly beneficial application of the method is in reduction of internal stress in a stack containing multiple layers of silicon. Typically, though not necessarily, the internal stress is a compressive stress, which often manifests as wafer bow. In some embodiments, the method reduces the internal stress of a work piece by depositing phosphorus doped silicon layers having low internal compressive stress or even tensile stress. The method and apparatus disclosed herein can be used to reduce compressive bow in stacks containing silicon.

    摘要翻译: 本文公开的方法和装置涉及制备半导体衬底上的电子器件的堆叠结构。 该方法的特别有益的应用是减少包含多层硅的堆叠中的内部应力。 通常,尽管不一定,内部应力是压缩应力,其通常表现为晶片弓。 在一些实施例中,该方法通过沉积具有低内部压缩应力或甚至拉伸应力的磷掺杂硅层来降低工件的内部应力。 本文公开的方法和装置可以用于减少包含硅的堆叠中的压缩弓。