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81.
公开(公告)号:US20200279913A1
公开(公告)日:2020-09-03
申请号:US16290165
申请日:2019-03-01
发明人: Mona A. Ebrish , Fee Li Lie , Nicolas Loubet , Gauri Karve , Indira Seshadri , Lawrence A. Clevenger , Leigh Anne H. Clevenger
IPC分类号: H01L29/06 , H01L21/02 , H01L29/66 , H01L29/08 , H01L29/165 , H01L29/78 , H01L27/088 , H01L21/8234
摘要: Embodiments of the invention are directed to a nanosheet field effect transistor (FET) device. A non-limiting example of the nanosheet FET device includes a stack of channel nanosheets over a substrate, along with a source or drain (S/D) trench in a predetermined region of the substrate. The predetermined region of the substrate includes a region over which a S/D region of the nanosheet FET is formed. The S/D region of the nanosheet FET is formed at ends of a bottommost one of the stack of channel nanosheets. An isolation barrier is formed in the S/D trench. The isolation barrier is configured to substantially prevent the S/D region from being electrically coupled to the substrate.
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82.
公开(公告)号:US10756203B2
公开(公告)日:2020-08-25
申请号:US16597502
申请日:2019-10-09
发明人: Julien Frougier , Ruilong Xie , Steven Bentley , Kangguo Cheng , Nicolas Loubet , Pietro Montanini
IPC分类号: H01L29/66 , H01L29/423 , H01L29/78
摘要: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.
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83.
公开(公告)号:US10727320B2
公开(公告)日:2020-07-28
申请号:US15858266
申请日:2017-12-29
申请人: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人: Shay Reboh , Emmanuel Augendre , Remi Coquand , Nicolas Loubet
IPC分类号: H01L29/66 , H01L29/78 , H01L29/165 , H01L29/06 , H01L29/08 , H01L29/417 , B82Y10/00 , H01L29/40 , H01L29/775
摘要: A method of manufacturing a field effect transistor is provided, including supplying a substrate surmounted by first, second, and third structures, the second structure arranged between the first and the third structures and including at least one first nano-object located away from the substrate, a part of the first nano-object being configured to form a channel area of the transistor; forming electrodes of the transistor including epitaxial growth of a first material to obtain a first continuity of matter made of the first material between the second structure and the first structure, and to obtain a second continuity of matter made of the first material between the second structure and the third structure; and epitaxial growth of a second material, starting from the first material, the second material having a lattice parameter different from a lattice parameter of the first material of the first and the second continuities.
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84.
公开(公告)号:US20200044058A1
公开(公告)日:2020-02-06
申请号:US16597502
申请日:2019-10-09
发明人: Julien Frougier , Ruilong Xie , Steven Bentley , Kangguo Cheng , Nicolas Loubet , Pietro Montanini
IPC分类号: H01L29/66 , H01L29/423 , H01L29/78
摘要: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.
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85.
公开(公告)号:US10553705B2
公开(公告)日:2020-02-04
申请号:US16226876
申请日:2018-12-20
发明人: Julien Frougier , Ruilong Xie , Steven Bentley , Kangguo Cheng , Nicolas Loubet , Pietro Montanini
IPC分类号: H01L29/66 , H01L29/423 , H01L29/78
摘要: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.
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公开(公告)号:US20190393076A1
公开(公告)日:2019-12-26
申请号:US16562098
申请日:2019-09-05
IPC分类号: H01L21/762 , H01L29/78 , H01L29/423 , H01L29/66 , H01L29/06 , H01L29/40
摘要: A semiconductor device is fabricated with a first layer of a first sacrificial material deposited over a surface of a substrate. A first set of layers of a second sacrificial material and a second set of layers of a channel material are deposited over the first layer. A liner is deposited in a first recess, which exposes a first connection end of a layer in the second set, where the first recess reaches into the substrate for at least a fraction of a total depth of the substrate. An insulator material is filled in the first recess and etched up to a stop depth, stopping the etching at a height above the surface of the substrate. The liner is removed from at least the first connection end of the layer in the second set. An electrical connection is formed with a source/drain structure using the first connection end.
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87.
公开(公告)号:US10388760B1
公开(公告)日:2019-08-20
申请号:US15898314
申请日:2018-02-16
发明人: Julien Frougier , Ruilong Xie , Steven Bentley , Kangguo Cheng , Nicolas Loubet , Pietro Montanini
IPC分类号: H01L29/66 , H01L29/78 , H01L29/423
摘要: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.
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公开(公告)号:US20190252508A1
公开(公告)日:2019-08-15
申请号:US16373242
申请日:2019-04-02
发明人: Julien Frougier , Nicolas Loubet , Ruilong Xie , Daniel Chanemougame , Ali Razavieh , Kangguo Cheng
IPC分类号: H01L29/43 , H01L49/00 , H01L21/3105 , H01L29/78 , H01L21/3213 , H01L23/525
CPC分类号: H01L29/435 , H01L21/31053 , H01L21/32139 , H01L23/525 , H01L27/228 , H01L27/2454 , H01L29/41791 , H01L29/66795 , H01L29/785 , H01L49/003 , H04L67/10
摘要: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.
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公开(公告)号:US20190252507A1
公开(公告)日:2019-08-15
申请号:US15894218
申请日:2018-02-12
发明人: Julien Frougier , Nicolas Loubet , Ruilong Xie , Daniel Chanemougame , Ali Razavieh , Kangguo Cheng
IPC分类号: H01L29/43 , H01L29/78 , H01L23/525 , H01L49/00 , H01L21/3105
CPC分类号: H01L29/435 , H01L21/31053 , H01L23/525 , H01L29/785 , H01L49/003 , H04L67/10
摘要: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a plurality of source/drains disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a plurality of trenches, each trench extending to a corresponding one of the plurality of source/drains. A trench contact is formed in each of the trenches in contact with the corresponding source/drain. A recess is formed in a portion of each trench contact below a top surface of the cap. A bi-stable resistive system (BRS) material is deposited in each recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch for each of the corresponding source/drains.
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公开(公告)号:US10262905B2
公开(公告)日:2019-04-16
申请号:US14867797
申请日:2015-09-28
发明人: Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Qing Liu , Nicolas Loubet , Scott Luning
IPC分类号: H01L21/84 , H01L21/8238 , H01L27/092 , H01L29/16 , H01L29/161 , H01L27/12 , H01L29/49 , H01L29/10
摘要: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.
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