公开(公告)号：US09177868B2

公开(公告)日：2015-11-03

申请号：US14228840

申请日：2014-03-28

Applicant: International Business Machines Corporation

Inventor： Unoh Kwon ,  Wing L. Lai ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Shahab Siddiqui

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823828 ,  H01L21/823857 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor structure by forming an oxide layer above a substrate; optionally annealing the oxide layer to densify the oxide layer; forming a first sacrificial gate above the substrate; removing the first dummy gate; optionally annealing the first gate oxide layer; and forming a first replacement metal gate above the gate oxide layer. In some embodiments selective nitridation may be performed during the annealing step.

Abstract translation: 一种通过在衬底上形成氧化层来制造半导体结构的方法; 任选地退火氧化物层以致密化氧化物层; 在所述衬底上形成第一牺牲栅极; 去除第一虚拟门; 可选地退火第一栅极氧化物层; 以及在所述栅极氧化物层上方形成第一替代金属栅极。 在一些实施方案中，可以在退火步骤期间进行选择性氮化。

公开(公告)号：US20150228748A1

公开(公告)日：2015-08-13

申请号：US14179121

申请日：2014-02-12

Applicant: International Business Machines Corporation

Inventor： Emre Alptekin ,  Unoh Kwon ,  Wing L. Lai ,  Zhengwen Li ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Reinaldo A. Vega

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/40 ,  H01L27/088

CPC classification number: H01L29/408 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

Abstract: A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion. After formation of gate spacers and a planarization dielectric layer, the second gate structure is replaced with a transient gate structure including a chemical oxide portion and a second high-k gate dielectric. A work-function metal layer and a conductive material portion can be formed in each gate electrode by replacement of semiconductor material portions. A gate electrode includes the planar silicon-based gate dielectric, the planar high-k gate dielectric, and a U-shaped high-k gate dielectric, and another gate electrode includes the chemical oxide portion and another U-shaped high-k gate dielectric.

Abstract translation: 在半导体材料层上形成第一栅极结构和第二栅极结构。 第一栅极结构包括平面硅基栅极电介质，平面高k栅极电介质，金属氮化物部分和第一半导体材料部分，并且第二栅极结构包括硅基电介质材料部分和第二半导体 材料部分。 在形成栅极间隔物和平坦化介电层之后，用包括化学氧化物部分和第二高k栅极电介质的瞬态栅极结构来代替第二栅极结构。 可以通过更换半导体材料部分在每个栅电极中形成功函数金属层和导电材料部分。 栅电极包括平面硅基栅极电介质，平面高k栅极电介质和U形高k栅极电介质，另一个栅电极包括化学氧化物部分和另一个U形高k栅极电介质 。

公开(公告)号：US09099393B2

公开(公告)日：2015-08-04

申请号：US13959375

申请日：2013-08-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDARIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Wing L. Lai ,  Vijay Narayanan ,  Ravikumar Ramachandran

IPC: H01L21/28 ,  H01L27/092

CPC classification number: H01L21/28229 ,  H01L21/28185 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7851

Abstract: A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.

Abstract translation: 一种用于半导体制造的方法包括在栅腔中的介电层上形成扩散阻挡层和含金属层中的至少一个。 执行第一退火以将元件从扩散阻挡层和含金属层中的至少一个扩散到电介质层中。 去除含金属层和扩散阻挡层。 执行第二次退火以调节介电层中的元件的扩散以提供栅极电介质区域。

公开(公告)号：US20140284721A1

公开(公告)日：2014-09-25

申请号：US14296522

申请日：2014-06-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Emre Alptekin ,  Ravikumar Ramachandran ,  Viraj Y. Sardesai ,  Reinaldo A. Vega

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes patterning a fin on a semiconductor substrate, depositing a local trench isolation (LTI) layer on the semiconductor substrate, patterning a gate stack over a channel region of the fin and over a portion of the LTI layer, depositing a first capping layer over exposed portions of the LTI layer, performing an etching process to remove oxide material from exposed portions of the fin, and epitaxially growing a semiconductor material from exposed portions of the fin to define active regions.

Abstract translation: 一种方法包括在半导体衬底上图案化翅片，在半导体衬底上沉积局部沟槽隔离层（LTI）层，在栅极的沟道区域和LTI层的一部分上图案化栅叠层;沉积第一覆盖层 在LTI层的暴露部分上，执行蚀刻工艺以从鳍的暴露部分去除氧化物材料，并且从鳍的暴露部分外延生长半导体材料以限定有源区。

公开(公告)号：US08815693B2

公开(公告)日：2014-08-26

申请号：US13747683

申请日：2013-01-23

Applicant: International Business Machines Corporation

Inventor： Emre Alptekin ,  Ravikumar Ramachandran ,  Viraj Y. Sardesai ,  Reinaldo A. Vega

IPC: H01L21/336 ,  H01L21/4763

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes patterning a fin on a semiconductor substrate, depositing a local trench isolation (LTI) layer on the semiconductor substrate, patterning a gate stack over a channel region of the fin and over a portion of the LTI layer, depositing a first capping layer over exposed portions of the LTI layer, performing an etching process to remove oxide material from exposed portions of the fin, and epitaxially growing a semiconductor material from exposed portions of the fin to define active regions.

Abstract translation: 一种方法包括在半导体衬底上图案化翅片，在半导体衬底上沉积局部沟槽隔离层（LTI）层，在栅极的沟道区域和LTI层的一部分上图案化栅叠层;沉积第一覆盖层 在LTI层的暴露部分上，执行蚀刻工艺以从鳍的暴露部分去除氧化物材料，并且从鳍的暴露部分外延生长半导体材料以限定有源区。

公开(公告)号：US20140151801A1

公开(公告)日：2014-06-05

申请号：US13689948

申请日：2012-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Balasubramanian S. Haran ,  Sanjay Mehta ,  Shom Ponoth ,  Ravikumar Ramachandran ,  Stefan Schmitz ,  Theodorus E. Standaert

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L29/42364 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method including providing a plurality of fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the plurality of fins and the nitride layer, removing a portion of the plurality of fins to form an opening, and forming a dielectric spacer on a sidewall of the opening. The method may also include filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer, removing the nitride layer to form a gap between the plurality of fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the plurality of fins and the fill material to widen.

Abstract translation: 一种方法，包括提供从半导体衬底蚀刻并被氧化物层和氮化物层覆盖的多个散热片，所述氧化物层位于所述多个散热片和所述氮化物层之间，去除所述多个翅片的一部分以形成 打开并在开口的侧壁上形成电介质间隔物。 该方法还可以包括用填充材料填充开口，其中填充材料的顶表面基本上与氮化物层的顶表面齐平，去除氮化物层以在多个翅片和填充材料之间形成间隙 ，其中所述填充材料具有在所述间隙上延伸的重新排列的几何形状，以及移除所述重新进入的几何形状并使所述多个翅片和所述填充材料之间的间隙变宽。

公开(公告)号：US20130175587A1

公开(公告)日：2013-07-11

申请号：US13780912

申请日：2013-02-28

Applicant: International Business Machines Corporation

Inventor： Ravikumar Ramachandran ,  Ying Li ,  Richard S. Wise

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7843

Abstract: A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure.

Abstract translation: 替代栅极堆叠的导电顶表面通过至少一个蚀刻相对于平坦化介电层的顶表面凹陷。 介电覆盖层沉积在平坦化电介质层和替代栅极堆叠的顶表面上，使得替代栅极堆叠上的介电顶盖层的一部分的顶表面相对于上述电介质层的另一部分垂直凹陷 平坦化介电层。 电介质覆盖层的垂直偏移可以与选择性通孔蚀刻工艺结合使用以形成自对准接触结构。

公开(公告)号：US20250107205A1

公开(公告)日：2025-03-27

申请号：US18371015

申请日：2023-09-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Albert M. Chu ,  Brent A. Anderson ,  Ravikumar Ramachandran

IPC: H01L29/417

Abstract: A semiconductor device is provided. The semiconductor device includes an active region, a gate, a gate contact formed on the gate, the gate contact overlapping in plan view with at least a portion of the active region, and a source/drain contact formed on the active region and adjacent to the gate contact. The gate contact is offset from a centerline of the gate in a direction away from the source/drain contact.

公开(公告)号：US20240321982A1

公开(公告)日：2024-09-26

申请号：US18189245

申请日：2023-03-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Julien Frougier ,  Nicolas Jean Loubet ,  Dechao Guo ,  Ravikumar Ramachandran

IPC: H01L29/417 ,  H01L23/522

CPC classification number: H01L29/41775 ,  H01L23/5226

Abstract: A transistor structure including a gate with a dielectric gate cap, a self-aligned source drain contact, where a topmost surface of the self-aligned source drain contact is substantially flush with a topmost surface of a first dielectric layer, a gate contact extending through the first dielectric layer, where a topmost surface of the gate contact is substantially flush with a topmost surface of a second dielectric layer, and a spacer surrounding the gate contact and physically separating it from the self-aligned source drain contact.

公开(公告)号：US20240145238A1

公开(公告)日：2024-05-02

申请号：US18050554

申请日：2022-10-28

Applicant: International Business Machines Corporation

Inventor： Reinaldo Vega ,  Shogo Mochizuki ,  Ruilong Xie ,  Julien Frougier ,  Ravikumar Ramachandran

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/0251 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775

Abstract: Embodiments of the invention include an isolation layer under a nanosheet stack of a transistor and a graded layer under the isolation layer. The graded layer includes an impurity gradient.