公开(公告)号：US09054127B2

公开(公告)日：2015-06-09

申请号：US14333555

申请日：2014-07-17

Applicant: International Business Machines Corporation

Inventor： Hemanth Jagannathan ,  Sanjay Mehta

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/49 ,  H01L29/66795 ,  H01L29/785

Abstract: A method including forming a dummy gate on a substrate, wherein the dummy gate includes an oxide, forming a pair of dielectric spacers on opposite sides of the dummy gate, and forming an inter-gate region above the substrate and in contact with at least one of the pair of dielectric spacers, the inter-gate region comprising a protective layer on top of a first oxide layer, wherein the protective layer comprises a material resistant to etching techniques designed to remove oxide. The method may further include removing the dummy gate to leave an opening, and forming a gate within the opening.

Abstract translation: 一种包括在基板上形成虚拟栅极的方法，其中所述伪栅极包括氧化物，在所述伪栅极的相对侧上形成一对电介质间隔物，以及在所述基板上形成栅极间区域并与至少一个 所述栅极间区域包括在第一氧化物层的顶部上的保护层，其中所述保护层包括耐蚀刻技术以防止氧化物的材料。 该方法还可以包括去除虚拟门以留下开口，并且在开口内形成门。

公开(公告)号：US20140327076A1

公开(公告)日：2014-11-06

申请号：US14333555

申请日：2014-07-17

Applicant: International Business Machines Corporation

Inventor： Hemanth Jagannathan ,  Sanjay Mehta

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L29/49 ,  H01L29/66795 ,  H01L29/785

Abstract: A method including forming a dummy gate on a substrate, wherein the dummy gate includes an oxide, forming a pair of dielectric spacers on opposite sides of the dummy gate, and forming an inter-gate region above the substrate and in contact with at least one of the pair of dielectric spacers, the inter-gate region comprising a protective layer on top of a first oxide layer, wherein the protective layer comprises a material resistant to etching techniques designed to remove oxide. The method may further include removing the dummy gate to leave an opening, and forming a gate within the opening.

公开(公告)号：US20140319611A1

公开(公告)日：2014-10-30

申请号：US14327598

申请日：2014-07-10

Applicant: International Business Machines Corporation

Inventor： Balasubramanian S. Haran ,  Sanjay Mehta ,  Shom Ponoth ,  Ravikumar Ramachandran ,  Stefan Schmitz ,  Theodorus E. Standaert

IPC: H01L29/423 ,  H01L27/12 ,  H01L27/088

CPC classification number: H01L29/42364 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/6681

Abstract: A structure including a first plurality of fins and a second plurality of fins etched from a semiconductor substrate, and a fill material located above the semiconductor substrate and between the first plurality of fins and the second plurality of fins, the fill material does not contact either the first plurality of fins or the second plurality of fins.

Abstract translation: 包括从半导体衬底蚀刻的第一多个散热片和第二多个散热片的结构以及位于半导体衬底上方以及第一组散热片和第二组散热片之间的填充材料，填充材料不接触 第一多个翅片或第二多个翅片。

公开(公告)号：US20140124873A1

公开(公告)日：2014-05-08

申请号：US13670748

申请日：2012-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hemanth Jagannathan ,  Sanjay Mehta

IPC: H01L29/423 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L29/49 ,  H01L29/66795 ,  H01L29/785

Abstract: A method including forming a dummy gate on a substrate, wherein the dummy gate includes an oxide, forming a pair of dielectric spacers on opposite sides of the dummy gate, and forming an inter-gate region above the substrate and in contact with at least one of the pair of dielectric spacers, the inter-gate region comprising a protective layer on top of a first oxide layer, wherein the protective layer comprises a material resistant to etching techniques designed to remove oxide. The method may further include removing the dummy gate to leave an opening, and forming a gate within the opening.

Abstract translation: 一种包括在基板上形成虚拟栅极的方法，其中所述伪栅极包括氧化物，在所述伪栅极的相对侧上形成一对电介质间隔物，以及在所述基板上形成栅极间区域并与至少一个 所述栅极间区域包括在第一氧化物层的顶部上的保护层，其中所述保护层包括耐蚀刻技术以防止氧化物的材料。 该方法还可以包括去除虚拟门以留下开口，并且在开口内形成门。

公开(公告)号：US09356121B2

公开(公告)日：2016-05-31

申请号：US14486128

申请日：2014-09-15

Applicant: International Business Machines Corporation

Inventor： Hemanth Jagannathan ,  Sanjay Mehta

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/423

CPC classification number: H01L29/518 ,  H01L21/02172 ,  H01L21/31051 ,  H01L21/823842 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7831

Abstract: After formation of a silicon nitride gate spacer and a silicon nitride liner overlying a disposable gate structure, a dielectric material layer is deposited, which includes a dielectric material that is not prone to material loss during subsequent exposure to wet or dry etch chemicals employed to remove disposable gate materials in the disposable gate structure. The dielectric material can be a spin-on dielectric material or can be a dielectric metal oxide material. The dielectric material layer and the silicon nitride liner are planarized to provide a planarized dielectric surface in which the disposable gate materials are physically exposed. Surfaces of the planarized dielectric layer is not recessed relative to surfaces of the silicon nitride layer during removal of the disposable gate materials and prior to formation of replacement gate structures, thereby preventing formation of metallic stringers.

Abstract translation: 在形成覆盖一次性栅极结构的氮化硅栅极隔离物和氮化硅衬垫之后，沉积介电材料层，其包括介电材料，其在随后暴露于用于除去的湿法或干法蚀刻化学品中不容易发生材料损失 一次性栅极材料在一次性栅极结构中。 介电材料可以是旋涂电介质材料，也可以是介电金属氧化物材料。 介电材料层和氮化硅衬垫被平坦化以提供其中一次性栅极材料物理暴露的平坦化电介质表面。 平面化电介质层的表面在去除一次性栅极材料期间以及在形成替代栅极结构之前不相对于氮化硅层的表面凹陷，从而防止形成金属桁条。

公开(公告)号：US08890255B2

公开(公告)日：2014-11-18

申请号：US13791545

申请日：2013-03-08

Applicant: International Business Machines Corporation

Inventor： Sivananda K. Kanakasabapathy ,  Sanjay Mehta ,  Hemanth Jagannathan

IPC: H01L21/70 ,  H01L29/78 ,  H01L27/088 ,  H01L21/82 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/82 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/785

Abstract: Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed.

Abstract translation: 公开了一种技术来将外部应力施加到源极/漏极半导体鳍状物侧壁区域上并将其锁定到半导体鳍片上，然后释放侧壁以用于随后的盐化和接触形成。 特别地，半导体的选定部分经受非晶化离子注入，其使半导体鳍片的选定部分的晶体结构相对于栅叠层下方的半导体鳍片的部分和各种衬垫封装。 形成至少一个应力衬垫，然后通过进行应力闭锁退火而发生应力记忆。 在该退火期间，发生错位取向晶体结构的重结晶。 去除至少一个应力衬垫，然后执行源极/漏极区域中的半导体鳍片的合并。

公开(公告)号：US08835237B2

公开(公告)日：2014-09-16

申请号：US13670748

申请日：2012-11-07

Applicant: International Business Machines Corporation

Inventor： Hemanth Jagannathan ,  Sanjay Mehta

IPC: H01L21/338

CPC classification number: H01L29/66545 ,  H01L29/49 ,  H01L29/66795 ,  H01L29/785

Abstract: A method including forming a dummy gate on a substrate, wherein the dummy gate includes an oxide, forming a pair of dielectric spacers on opposite sides of the dummy gate, and forming an inter-gate region above the substrate and in contact with at least one of the pair of dielectric spacers, the inter-gate region comprising a protective layer on top of a first oxide layer, wherein the protective layer comprises a material resistant to etching techniques designed to remove oxide. The method may further include removing the dummy gate to leave an opening, and forming a gate within the opening.

Abstract translation: 一种包括在基板上形成虚拟栅极的方法，其中所述伪栅极包括氧化物，在所述伪栅极的相对侧上形成一对电介质间隔物，以及在所述基板上形成栅极间区域并与至少一个 所述栅极间区域包括在第一氧化物层的顶部上的保护层，其中所述保护层包括耐蚀刻技术以防止氧化物的材料。 该方法还可以包括去除虚拟门以留下开口，并且在开口内形成门。

公开(公告)号：US20140239420A1

公开(公告)日：2014-08-28

申请号：US13776324

申请日：2013-02-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Sanjay Mehta ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/66803

Abstract: A method of forming a FinFET structure which includes forming fins on a semiconductor substrate; forming a gate wrapping around at least one of the fins, the gate having a first surface and an opposing second surface facing the fins; depositing a hard mask on a top of the gate; angle implanting nitrogen into the first and second surfaces of the gate so as to form a nitrogen-containing layer in the gate that is below and in direct contact with the hard mask on top of the gate; forming spacers on the gate and in contact with the nitrogen-containing layer; and epitaxially depositing silicon on the at least one fin so as to form a raised source/drain. Also disclosed is a FinFET structure.

Abstract translation: 一种形成FinFET结构的方法，其包括在半导体衬底上形成翅片; 形成围绕所述翅片中的至少一个包围的门，所述门具有面对所述翅片的第一表面和相对的第二表面; 在门的顶部沉积硬掩模; 将氮注入到栅极的第一和第二表面中，以便在栅极中形成含氮层，该栅极位于门的顶部以下且与硬掩模直接接触; 在栅极上形成间隔物并与含氮层接触; 并且在所述至少一个翅片上外延地沉积硅以形成升高的源极/漏极。 还公开了FinFET结构。

公开(公告)号：US20140151801A1

公开(公告)日：2014-06-05

申请号：US13689948

申请日：2012-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Balasubramanian S. Haran ,  Sanjay Mehta ,  Shom Ponoth ,  Ravikumar Ramachandran ,  Stefan Schmitz ,  Theodorus E. Standaert

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L29/42364 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method including providing a plurality of fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the plurality of fins and the nitride layer, removing a portion of the plurality of fins to form an opening, and forming a dielectric spacer on a sidewall of the opening. The method may also include filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer, removing the nitride layer to form a gap between the plurality of fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the plurality of fins and the fill material to widen.

Abstract translation: 一种方法，包括提供从半导体衬底蚀刻并被氧化物层和氮化物层覆盖的多个散热片，所述氧化物层位于所述多个散热片和所述氮化物层之间，去除所述多个翅片的一部分以形成 打开并在开口的侧壁上形成电介质间隔物。 该方法还可以包括用填充材料填充开口，其中填充材料的顶表面基本上与氮化物层的顶表面齐平，去除氮化物层以在多个翅片和填充材料之间形成间隙 ，其中所述填充材料具有在所述间隙上延伸的重新排列的几何形状，以及移除所述重新进入的几何形状并使所述多个翅片和所述填充材料之间的间隙变宽。

公开(公告)号：US20160064218A1

公开(公告)日：2016-03-03

申请号：US14925372

申请日：2015-10-28

Applicant: International Business Machines Corporation

Inventor： Donald Francis Canaperi ,  Alfred Grill ,  Sanjay Mehta ,  Son Van Nguyen ,  Deepika Priyadarshini ,  Hosadurga Shobha ,  Matthew T. Shoudy

IPC: H01L21/02

CPC classification number: H01L21/02274 ,  C23C16/345 ,  C23C16/401 ,  C23C16/45523 ,  C23C16/45525 ,  C23C16/50 ,  H01L21/02123 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02214 ,  H01L21/02219 ,  H01L21/02299 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53276 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/42364 ,  H01L29/4983 ,  H01L29/511 ,  H01L29/513 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.