公开(公告)号：US07023041B2

公开(公告)日：2006-04-04

申请号：US10341187

申请日：2003-01-13

Applicant: Giuseppe La Rosa ,  Thomas W. Dyer ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens ,  Alvin W. Strong

Inventor： Giuseppe La Rosa ,  Thomas W. Dyer ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens ,  Alvin W. Strong

IPC: H01L27/108 ,  H01L29/76

CPC classification number: H01L29/945 ,  H01L27/10861 ,  H01L27/10894 ,  H01L29/66181

Abstract: A versatile structure is formed, based on a deep trench, vertical transistor DRAM cell, that forms a conductive extension of the trench electrode in an elongated trench that contacts the lower electrode of the vertical transistor. The structure can be used as a capacitor, as a discrete transistor as a single-transistor amplifier or as a building block for more complex circuits.

Abstract translation: 基于深沟槽垂直晶体管DRAM单元形成通用结构，其在与垂直晶体管的下电极接触的细长沟槽中形成沟槽电极的导电延伸。 该结构可以用作电容器，作为单晶体管放大器的分立晶体管或作为更复杂电路的构建块。

公开(公告)号：US08889504B2

公开(公告)日：2014-11-18

申请号：US13364753

申请日：2012-02-02

Applicant: Thomas W Dyer ,  Haining S Yang

Inventor： Thomas W Dyer ,  Haining S Yang

IPC: H01L21/8239 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/7846 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/16 ,  H01L29/167 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7845

Abstract: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. A method of forming a semiconductor structure includes forming sidewalls and spacers adjacent to a gate stack structure, and forming a recess in the gate stack structure. The method further includes epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure. The straining material is Si:C and the gate stack structure is a PFET gate stack structure. The straining material is grown above and covering a top surface of the sidewalls and the spacers.

Abstract translation: 提供了具有施加于其上的拉伸和/或压缩应变的半导体器件及其制造方法。 一种形成半导体结构的方法包括：形成邻近栅叠层结构的侧壁和隔离层，以及在栅叠层结构中形成凹陷。 该方法还包括在栅极堆叠结构的多晶硅层上以及在栅极堆叠结构的凹槽中外延生长应变材料。 应变材料是Si：C，栅极堆叠结构是PFET栅极堆叠结构。 应变材料生长在侧壁和间隔物的顶表面上方并覆盖其顶表面。

公开(公告)号：US08697528B2

公开(公告)日：2014-04-15

申请号：US13615955

申请日：2012-09-14

Applicant: Thomas W. Dyer

Inventor： Thomas W. Dyer

IPC: H01L21/336

CPC classification number: H01L29/6656 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7848

Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

Abstract translation: 公开了一种结合外延​​沉积的源/漏半导体膜的晶体管和用于形成晶体管的方法。 晶体蚀刻用于在硅衬底中的沟道区和沟槽隔离区之间形成凹陷。 每个凹部具有与沟道区相邻的第一轮廓和具有与沟槽隔离区相邻的第二轮廓的第一侧。 晶体蚀刻确保第二轮廓成角度，使得所有暴露的凹部表面都包含硅。 因此，可以通过外延沉积而不形成凹坑来填充凹部。 可以使用附加的工艺步骤来确保凹部的第一侧形成有增强通道区域中的期望应力的不同轮廓。

公开(公告)号：US08377785B2

公开(公告)日：2013-02-19

申请号：US13080903

申请日：2011-04-06

Applicant: Thomas W. Dyer

Inventor： Thomas W. Dyer

IPC: H01L21/336

CPC classification number: H01L29/6656 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7848

Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

Abstract translation: 公开了一种结合外延​​沉积的源/漏半导体膜的晶体管和用于形成晶体管的方法。 晶体蚀刻用于在硅衬底中的沟道区和沟槽隔离区之间形成凹陷。 每个凹部具有与沟道区相邻的第一轮廓和具有与沟槽隔离区相邻的第二轮廓的第一侧。 晶体蚀刻确保第二轮廓成角度，使得所有暴露的凹部表面都包含硅。 因此，可以通过外延沉积而不形成凹坑来填充凹部。 可以使用附加的工艺步骤来确保凹部的第一侧形成有增强通道区域中的期望应力的不同轮廓。

公开(公告)号：US20120135591A1

公开(公告)日：2012-05-31

申请号：US13364753

申请日：2012-02-02

Applicant: Thomas W. DYER ,  Haining S. YANG

Inventor： Thomas W. DYER ,  Haining S. YANG

IPC: H01L21/28

CPC classification number: H01L29/7846 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/16 ,  H01L29/167 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7845

Abstract: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. A method of forming a semiconductor structure includes forming sidewalls and spacers adjacent to a gate stack structure, and forming a recess in the gate stack structure. The method further includes epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure. The straining material is Si:C and the gate stack structure is a PFET gate stack structure. The straining material is grown above and covering a top surface of the sidewalls and the spacers.

Abstract translation: 提供了具有施加于其上的拉伸和/或压缩应变的半导体器件及其制造方法。 一种形成半导体结构的方法包括：形成邻近栅叠层结构的侧壁和隔离层，以及在栅叠层结构中形成凹陷。 该方法还包括在栅极堆叠结构的多晶硅层上以及在栅极堆叠结构的凹槽中外延生长应变材料。 应变材料是Si：C，栅极堆叠结构是PFET栅极堆叠结构。 应变材料生长在侧壁和间隔物的顶表面上方并覆盖其顶表面。

公开(公告)号：US08159031B2

公开(公告)日：2012-04-17

申请号：US12709873

申请日：2010-02-22

Applicant: Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

Inventor： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

IPC: H01L27/12

CPC classification number: H01L29/0653 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

Abstract: An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate.

Abstract translation: 提供了一种改进的绝缘体上半导体（SOI）衬底，其包含在不同深度处的图案化掩埋绝缘体层。 具体而言，SOI衬底具有基本平坦的上表面，并且包括：（1）不包含任何埋入绝缘体的第一区域，（2）第一区域，其包含第一深度处的图案化掩埋绝缘体层的第一部分 从SOI衬底的平坦的上表面），和（3）第二深度大于第二深度的第二深度上包含图案化的掩埋绝缘体层的第二部分的第三区域。 可以在SOI衬底中形成一个或多个场效应晶体管（FET）。 例如，FET可以包括：SOI衬底的第一区域中的沟道区域，SOI衬底的第二区域中的源极和漏极区域以及SOI衬底的第三区域中的源极/漏极延伸区域。

公开(公告)号：US08110464B2

公开(公告)日：2012-02-07

申请号：US12048291

申请日：2008-03-14

Applicant: Thomas W. Dyer ,  Herbert L. Ho ,  Ravi M. Todi

Inventor： Thomas W. Dyer ,  Herbert L. Ho ,  Ravi M. Todi

IPC: H01L21/8242

CPC classification number: H01L29/945 ,  H01L21/3086 ,  H01L21/84 ,  H01L27/1087 ,  H01L29/66181

Abstract: An SOI layer has an initial trench extending therethrough, prior to deep trench etch. An oxidation step, such as thermal oxidation is performed to form a band of oxide on an inner periphery of the SOI layer to protect it during a subsequent RIE step for forming a deep trench. The initial trench may stop on BOX underlying the SOI. The band of oxide may also protect the SOI during buried plate implant or gas phase doping.

Abstract translation: 在深沟槽蚀刻之前，SOI层具有穿过其延伸的初始沟槽。 执行氧化步骤，例如热氧化，以在SOI层的内周上形成氧化带，以在随后的用于形成深沟槽的RIE步骤中保护它。 初始沟槽可能停在SOI上的BOX上。 在掩埋板植入或气相掺杂期间，氧化物带也可以保护SOI。

公开(公告)号：US20110163387A1

公开(公告)日：2011-07-07

申请号：US13050219

申请日：2011-03-17

Applicant: Kyoung Woo Lee ,  Ja Hum Ku ,  Taehoon Lee ,  Seung-Man Choi ,  Thomas W. Dyer

Inventor： Kyoung Woo Lee ,  Ja Hum Ku ,  Taehoon Lee ,  Seung-Man Choi ,  Thomas W. Dyer

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823871 ,  H01L29/7843

Abstract: CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.

Abstract translation: 提供CMOS（互补金属氧化物半导体）制造技术以形成具有非重叠，自对准的双应力衬垫结构的DSL（双应力衬垫）半导体器件。

公开(公告)号：US07906384B2

公开(公告)日：2011-03-15

申请号：US12047379

申请日：2008-03-13

Applicant: Thomas W Dyer

Inventor： Thomas W Dyer

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/28035 ,  H01L21/324 ,  H01L29/4916 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7847

Abstract: A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices to enhance channel strain. The method includes relaxing a gate structure using a low temperature thermal creep process to enhance channel strain. The gate structure undergoes a plastic deformation during the low temperature thermal creep process.

Abstract translation: 具有施加拉伸和/或压缩应变的半导体器件和制造半导体器件以增强通道应变的方法。 该方法包括使用低温热蠕变过程来松弛栅极结构以增强通道应变。 门结构在低温热蠕变过程中经历塑性变形。

公开(公告)号：US07884448B2

公开(公告)日：2011-02-08

申请号：US12500396

申请日：2009-07-09

Applicant: Thomas W. Dyer ,  Haining S. Yang

Inventor： Thomas W. Dyer ,  Haining S. Yang

IPC: H01L29/04

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/04 ,  H01L29/66795 ,  H01L29/7853

Abstract: The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.

Abstract translation: 本发明涉及高性能三维（3D）场效应晶体管（FET）。 具体而言，可以使用具有沿着第一组等效晶面中的一个取向的底表面和沿着第二不同组的等效晶面取向的多个附加表面的3D半导体结构，以形成具有载体通道定向的高性能3D FET 沿着第二个不同组的等效晶面。 更重要的是，这种3D半导体结构可以容易地在具有底表面和多个附加表面的附加3D半导体结构的同一衬底上形成，所述另外的三维半导体结构全部沿着第一组等效晶面取向。 附加的3D半导体结构可以用于形成附加的3D FET，其与上述3D FET互补，并且具有沿着第一组等效晶面取向的载流子通道。