公开(公告)号：US20140145201A1

公开(公告)日：2014-05-29

申请号：US13689574

申请日：2012-11-29

Applicant: AVOGY, INC.

Inventor： Hui Nie ,  Andrew P. Edwards ,  David P. Bour ,  Isik C. Kizilyalli ,  Richard J. Brown ,  Thomas R. Prunty

IPC: H01L29/78 ,  H01L29/20 ,  H01L21/36

CPC classification number: H01L29/2003 ,  H01L29/66446 ,  H01L29/8083

Abstract: A semiconductor structure includes a III-nitride substrate and a first III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The semiconductor structure also includes a first III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial layer and a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure. The semiconductor structure further includes a second III-nitride epitaxial layer coupled to the first III-nitride epitaxial structure. The second III-nitride epitaxial layer is of a second conductivity type and is not electrically connected to the second III-nitride epitaxial structure.

Abstract translation: 半导体结构包括III族氮化物衬底和与III族氮化物衬底耦合的第一导电类型的第一III族氮化物外延层。 半导体结构还包括耦合到第一III族氮化物外延层的第一导电类型的第一III族氮化物外延结构和耦合到第一III族氮化物外延结构的第一导电类型的第二III族氮化物外延结构。 半导体结构还包括耦合到第一III族氮化物外延结构的第二III族氮化物外延层。 第二III族氮化物外延层是第二导电类型并且不与第二III族氮化物外延结构电连接。

公开(公告)号：US20170133481A1

公开(公告)日：2017-05-11

申请号：US15156979

申请日：2016-05-17

Applicant: Avogy, Inc.

Inventor： Isik C. Kizilyalli ,  Dave P. Bour ,  Thomas R. Prunty ,  Gangfeng Ye

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/04 ,  H01L29/861 ,  H01L29/20

Abstract: A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.

公开(公告)号：US09502544B2

公开(公告)日：2016-11-22

申请号：US14815780

申请日：2015-07-31

Applicant: AVOGY, INC.

Inventor： Isik C. Kizilyalli ,  Linda Romano ,  David P. Bour

IPC: H01L29/15 ,  H01L29/66 ,  H01L29/78 ,  H01L29/808 ,  H01L29/20

CPC classification number: H01L29/66924 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/7832 ,  H01L29/8083

Abstract: A vertical JFET includes a III-nitride substrate and a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer has a first dopant concentration. The vertical JFET also includes a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer. The III-nitride epitaxial structure includes a set of channels of the first conductivity type and having a second dopant concentration, a set of sources of the first conductivity type, having a third dopant concentration greater than the first dopant concentration, and each characterized by a contact surface, and a set of regrown gates interspersed between the set of channels. An upper surface of the set of regrown gates is substantially coplanar with the contact surfaces of the set of sources.

Abstract translation: 垂直JFET包括III族氮化物衬底和与III族氮化物衬底耦合的第一导电类型的III族氮化物外延层。 第一III族氮化物外延层具有第一掺杂剂浓度。 垂直JFET还包括耦合到第一III族氮化物外延层的III族氮化物外延结构。 III族氮化物外延结构包括一组第一导电类型的沟道并且具有第二掺杂剂浓度，第一导电类型的一组源，其具有大于第一掺杂剂浓度的第三掺杂剂浓度，并且各自的特征在于： 接触表面，以及一组重新生长的门，散布在通道组之间。 该组再生栅极的上表面与该组源的接触表面基本共面。

公开(公告)号：USD762573S1

公开(公告)日：2016-08-02

申请号：US29525732

申请日：2015-05-01

Applicant: Avogy, Inc.

Designer： Yves Béhar ,  Noah Murphy-Reinhertz ,  Diana Chang ,  Darin Smedberg ,  Frederick Allen Stillman

公开(公告)号：US09391179B2

公开(公告)日：2016-07-12

申请号：US14604606

申请日：2015-01-23

Applicant: Avogy, Inc.

Inventor： Donald R. Disney

IPC: H01L21/04 ,  H01L29/66 ,  H01L29/808

CPC classification number: H01L29/66909 ,  H01L21/04 ,  H01L29/66462 ,  H01L29/66924 ,  H01L29/8083

Abstract: An embodiment of a vertical power device includes a III-nitride substrate, a drift region coupled to the III-nitride substrate and comprising a III-nitride material of a first conductivity type, and a channel region coupled to the drift region and comprising a III-nitride material of the first conductivity type. The vertical power device also includes a source region coupled to the channel region and comprising a III-nitride material of the first conductivity type, and a gate region coupled to the channel region. The gate region includes a III-nitride material of a second conductivity type. The vertical power device further includes a source-coupled region coupled to the drift region and electrically connected with the source region. The source-coupled region includes a III-nitride material of the second conductivity type.

公开(公告)号：US09368582B2

公开(公告)日：2016-06-14

申请号：US14071032

申请日：2013-11-04

Applicant: AVOGY, INC.

Inventor： Isik C. Kizilyalli ,  David P. Bour ,  Thomas R. Prunty ,  Gangfeng Ye

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/861 ,  H01L21/02 ,  H01L21/76 ,  H01L29/04 ,  H01L29/06

CPC classification number: H01L29/66204 ,  H01L21/02389 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02634 ,  H01L21/7605 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/861 ,  H01L29/8613

Abstract: An electronic device includes a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the direction of between 0.15° and 0.65°. The electronic device also includes a first epitaxial layer coupled to the III-V substrate and a second epitaxial layer coupled to the first epitaxial layer. The electronic device further includes a first contact in electrical contact with the substrate and a second contact in electrical contact with the second epitaxial layer.

Abstract translation: 一种电子器件包括具有六方晶系结构的III-V衬底和与生长表面垂直的III-V衬底，其特征在于从<0001>方向在0.15°至0.65°之间的取向偏差。 电子器件还包括耦合到III-V衬底的第一外延层和耦合到第一外延层的第二外延层。 电子器件还包括与衬底电接触的第一触点和与第二外延层电接触的第二触点。

公开(公告)号：US09330918B2

公开(公告)日：2016-05-03

申请号：US14558393

申请日：2014-12-02

Applicant: Avogy, Inc.

Inventor： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  David P. Bour ,  Richard J. Brown ,  Thomas R. Prunty

IPC: H01L21/265 ,  H01L29/66 ,  H01L29/808 ,  H01L29/868 ,  H01L29/872 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L21/2654 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/2003 ,  H01L29/66143 ,  H01L29/6631 ,  H01L29/66446 ,  H01L29/66856 ,  H01L29/8083 ,  H01L29/868 ,  H01L29/872

Abstract: A method of making an edge terminated semiconductor device includes providing a GaN substrate having a GaN epitaxial layer grown thereon and exposing a portion of the GaN epitaxial layer to ion implantation. The energy dose is selected to provide a resistivity that is at least 90% of maximum achievable resistivity. The method also includes depositing a conductive layer over a portion of the implanted region.

Abstract translation: 制造边缘端接的半导体器件的方法包括提供其上生长有GaN外延层的GaN衬底，并将GaN外延层的一部分暴露于离子注入。 选择能量剂量以提供至少达到最大可实现电阻率的90％的电阻率。 该方法还包括在植入区域的一部分上沉积导电层。

公开(公告)号：US09324645B2

公开(公告)日：2016-04-26

申请号：US13901546

申请日：2013-05-23

Applicant: AVOGY, INC.

Inventor： Donald R. Disney ,  Hemal N. Shah

IPC: H01L31/0256 ,  H01L23/495 ,  H01L29/861 ,  H01L29/20 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L23/49541 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L29/2003 ,  H01L29/8611 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076

Abstract: An electronic package includes a leadframe and a plurality of pins. The electronic package also includes a first gallium nitride (GaN) transistor comprising a source, gate, and drain and a second GaN transistor comprising a source, gate, and drain. The source of the first GaN transistor is electrically connected to the leadframe and the drain of the second GaN transistor is electrically connected to the leadframe. The electronic package further includes a first GaN diode comprising an anode and cathode and a second GaN diode comprising an anode and cathode. The anode of the first GaN diode is electrically connected to the leadframe and the cathode of the second GaN diode is electrically connected to the leadframe.

Abstract translation: 电子封装包括引线框和多个引脚。 电子封装还包括包括源极，栅极和漏极的第一氮化镓（GaN）晶体管和包括源极，栅极和漏极的第二GaN晶体管。 第一GaN晶体管的源极电连接到引线框架，并且第二GaN晶体管的漏极电连接到引线框架。 电子封装还包括包括阳极和阴极的第一GaN二极管和包括阳极和阴极的第二GaN二极管。 第一GaN二极管的阳极电连接到引线框架，并且第二GaN二极管的阴极电连接到引线框架。

公开(公告)号：US09324607B2

公开(公告)日：2016-04-26

申请号：US14815751

申请日：2015-07-31

Applicant: AVOGY, INC.

Inventor： Patrick James Lazlo Hyland ,  Brian Joel Alvarez ,  Donald R. Disney

IPC: H01L21/768 ,  H01L21/283 ,  H01L23/528 ,  H01L29/20 ,  H01L23/532 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L23/495 ,  H01L23/482 ,  H01L23/00

CPC classification number: H01L21/7685 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/76865 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/528 ,  H01L23/53204 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L29/2003 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/0518 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/291 ,  H01L2224/29116 ,  H01L2224/32245 ,  H01L2224/83192 ,  H01L2224/83815 ,  H01L2224/9221 ,  H01L2224/9222 ,  H01L2224/92242 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A method for fabricating a vertical gallium nitride (GaN) power device can include providing a GaN substrate with a top surface and a bottom surface, forming a device layer coupled to the top surface of the GaN substrate, and forming a metal contact on a top surface of the vertical GaN power device. The method can further include forming a backside metal by forming an adhesion layer coupled to the bottom surface of the GaN substrate, forming a diffusion barrier coupled to the adhesion layer, and forming a protection layer coupled to the diffusion barrier. The vertical GaN power device can be configured to conduct electricity between the metal contact and the backside metal.

公开(公告)号：US09318619B2

公开(公告)日：2016-04-19

申请号：US14606822

申请日：2015-01-27

Applicant: Avogy, Inc.

Inventor： Donald R. Disney ,  Hui Nie ,  Isik C. Kizilyalli ,  Richard J. Brown

IPC: H01L29/808 ,  H01L29/70 ,  H01L29/40 ,  H01L29/66 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/8083 ,  H01L29/0623 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/66909 ,  H01L29/66924

Abstract: A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.