公开(公告)号：US06218245B1

公开(公告)日：2001-04-17

申请号：US09198654

申请日：1998-11-24

申请人： Qi Xiang ,  Xiao-Yu Li

发明人： Qi Xiang ,  Xiao-Yu Li

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/105 ,  H01L27/11558 ,  Y10S438/91

摘要： A method for fabricating a high-density and high-reliability EEPROM device includes providing a semiconductor substrate having both an EEPROM cell region, and a peripheral MOS transistor region. A gate oxide layer is formed to overlie the peripheral MOS transistor region and the EEPROM cell region. A tunnel oxide region is formed to overlie a portion of the EEPROM cell region. Then, a polycrystalline silicon layer is formed to overlie both the gate oxide layer and the tunnel oxide region. A deuterium annealing process is then carried out to anneal the gate oxide layer and the tunnel oxide region. The polycrystalline silicon layer is patterned to form numerous gate electrodes including gate electrodes for peripheral transistors, floating-gate transistors, and read and write transistors in the EEPROM cell.

摘要翻译： 一种用于制造高密度和高可靠性EEPROM器件的方法包括提供具有EEPROM单元区域和外围MOS晶体管区域的半导体衬底。 形成栅极氧化层以覆盖外围MOS晶体管区域和EEPROM单元区域。 形成隧道氧化物区域以覆盖EEPROM单元区域的一部分。 然后，形成多晶硅层以覆盖栅极氧化物层和隧道氧化物区域两者。 然后进行氘退火处理以退火栅极氧化物层和隧道氧化物区域。 图案化多晶硅层以形成多个栅电极，其包括用于外围晶体管的栅电极，浮栅晶体管以及EEPROM单元中的读写晶体管。

公开(公告)号：US6087696A

公开(公告)日：2000-07-11

申请号：US86437

申请日：1998-05-28

申请人： Xiao-Yu Li ,  Qi Xiang ,  Sunil D. Mehta

发明人： Xiao-Yu Li ,  Qi Xiang ,  Sunil D. Mehta

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L29/51 ,  H01L29/788

CPC分类号： H01L21/28194 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/513 ,  H01L29/517 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/518

摘要： An improved EEPROM cell structure and a method of fabricating the same is provided so as to improve data retention. The EEPROM cell includes a stacked dielectric structure consisting of a thin tunnel oxide layer and a high-k dielectric layer to function as the tunneling dielectric barrier so as to suppress leakage current.

摘要翻译： 提供了改进的EEPROM单元结构及其制造方法，以便改善数据保留。 EEPROM单元包括由薄的隧道氧化物层和高k电介质层构成的叠层电介质结构，用作隧道电介质势垒，以便抑制漏电流。

公开(公告)号：US6060377A

公开(公告)日：2000-05-09

申请号：US306874

申请日：1999-05-07

申请人： Qi Xiang ,  Scott A. Bell ,  Chih-Yuh Yang

发明人： Qi Xiang ,  Scott A. Bell ,  Chih-Yuh Yang

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/32139 ,  H01L21/0338 ,  H01L21/28123 ,  H01L29/6659

摘要： A polysilicon structure is fabricated with a reduced length that is beyond that achievable from photolithography by using a silicidation anneal to control the reduced length. Generally, the present invention includes a step of forming a masking polysilicon structure having a first predetermined length defined by sidewalls on ends of the first predetermined length of the masking polysilicon structure. The present invention also includes a step of depositing a layer of metal on the sidewalls of the masking polysilicon structure. The layer of metal has a predetermined thickness. The layer of metal reacts with the masking polysilicon structure at the sidewalls of the masking polysilicon structure in a silicidation anneal to form metal silicide. The masking polysilicon structure has a second predetermined length that is reduced from the first predetermined length when the metal silicide has consumed into the sidewalls of the masking polysilicon structure after the silicidation anneal. The second predetermined length depends on the predetermined thickness of the layer of metal deposited on the sidewalls of the masking polysilicon structure. The masking polysilicon structure has the second predetermined length and is used as a mask for etching a first layer of polysilicon to form the polysilicon structure from the first layer of polysilicon. The remaining polysilicon structure after this etch has the reduced length that is substantially equal to the second predetermined length of the masking polysilicon structure. The present invention may be used to particular advantage when the polysilicon structure having the reduced length forms a gate electrode of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

摘要翻译： 通过使用硅化退火来控制缩短的长度，制造出具有减小的长度的多晶硅结构，其超过通过光刻实现的结果。 通常，本发明包括形成具有由掩模多晶硅结构的第一预定长度的端部上的侧壁限定的第一预定长度的掩模多晶硅结构的步骤。 本发明还包括在掩模多晶硅结构的侧壁上沉积金属层的步骤。 金属层具有预定的厚度。 金属层在硅化退火中在掩模多晶硅结构的侧壁处与掩模多晶硅结构反应以形成金属硅化物。 掩模多晶硅结构具有第二预定长度，当在硅化退火之后金属硅化物消耗到掩模多晶硅结构的侧壁时，该第二预定长度从第一预定长度减小。 第二预定长度取决于沉积在掩模多晶硅结构的侧壁上的金属层的预定厚度。 掩模多晶硅结构具有第二预定长度，并且用作蚀刻第一多晶硅层的掩模，以从第一多晶硅层形成多晶硅结构。 在该蚀刻之后的剩余多晶硅结构具有基本上等于掩模多晶硅结构的第二预定长度的减小的长度。 当具有减小的长度的多晶硅结构形成MOSFET（金属氧化物半导体场效应晶体管）的栅电极时，本发明可以特别有利。

公开(公告)号：US08804407B1

公开(公告)日：2014-08-12

申请号：US13181219

申请日：2011-07-12

申请人： Jun Liu ,  Albert Ratnakumar ,  Irfan Rahim ,  Qi Xiang

发明人： Jun Liu ,  Albert Ratnakumar ,  Irfan Rahim ,  Qi Xiang

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  H03K2217/0054

摘要： An IC that includes a memory cell and a pass gate coupled to the memory cell, where the pass gate includes a PMOS transistor, is described. In one implementation, the PMOS transistor has a negative threshold voltage. In one implementation, the memory cell includes thick oxide transistors.

摘要翻译： 描述了包括耦合到存储器单元的存储单元和通过栅极的IC，其中栅极包括PMOS晶体管。 在一个实现中，PMOS晶体管具有负阈值电压。 在一个实现中，存储单元包括厚的氧化物晶体管。

公开(公告)号：US08735983B2

公开(公告)日：2014-05-27

申请号：US12324791

申请日：2008-11-26

申请人： Jun Liu ,  Albert Ratnakumar ,  Qi Xiang ,  Jeffrey Xiaoqi Tung

发明人： Jun Liu ,  Albert Ratnakumar ,  Qi Xiang ,  Jeffrey Xiaoqi Tung

IPC分类号： H01L21/02 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49

CPC分类号： H01L21/823842 ,  H01L21/28 ,  H01L21/28061 ,  H01L29/49 ,  H01L29/4983 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/7833

摘要： Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor.

摘要翻译： 提供了金属氧化物半导体晶体管。 可以在半导体衬底上形成金属氧化物半导体晶体管。 源极和漏极区可以形成在衬底中。 可以在源极和漏极区域之间形成诸如高K电介质的栅极绝缘体。 栅极可以由多个栅极导体形成。 栅极导体可以是具有不同功函数的金属。 栅极导体中的第一个可以形成与电介质间隔物相邻的一对边缘栅极导体。 边缘栅极导体之间​​的开口可以用第二栅极导体填充以形成中心栅极导体。 可以在制造金属氧化物半导体晶体管中使用自对准栅极形成工艺。

公开(公告)号：US08735050B2

公开(公告)日：2014-05-27

申请号：US13567233

申请日：2012-08-06

申请人： Lei Yuan ,  Hidekazu Yoshida ,  Jongwook Kye ,  Qi Xiang ,  Mahbub Rashed

发明人： Lei Yuan ,  Hidekazu Yoshida ,  Jongwook Kye ,  Qi Xiang ,  Mahbub Rashed

IPC分类号： G03F1/00 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G03F7/70466 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuits and methods for fabricating integrated circuits are provided. One method includes creating a master pattern layout including first and second adjacent cells. The first adjacent cell has a first border pin with a first routing line. The second adjacent cell has a second border pin with a second routing line. The first and second routing lines overlap to define an edge-edge stitch to couple the first and second border pins. The master pattern layout is decomposed into sub-patterns.

摘要翻译： 提供了用于制造集成电路的集成电路和方法。 一种方法包括创建包括第一和第二相邻单元格的主图案布局。 第一相邻单元具有带有第一路由线的第一边界引脚。 第二相邻单元具有带有第二路由线的第二边界引脚。 第一和第二路由线重叠以限定边缘线迹以耦合第一和第二边界引脚。 主模式布局被分解为子模式。

公开(公告)号：US08138791B1

公开(公告)日：2012-03-20

申请号：US12694603

申请日：2010-01-27

申请人： Albert Ratnakumar ,  Jun Liu ,  Jeffrey Xiaoqi Tung ,  Qi Xiang

发明人： Albert Ratnakumar ,  Jun Liu ,  Jeffrey Xiaoqi Tung ,  Qi Xiang

IPC分类号： H03K19/177

CPC分类号： H03K19/0008 ,  H01L27/11807 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

摘要： Integrated circuits with stressed transistors are provided. Stressing transistors may increase transistor threshold voltage without the need to increase channel doping. Stressing transistors may reduce total leakage currents. It may be desirable to compressively stress N-channel metal-oxide-semiconductor (NMOS) transistors and tensilely stress P-channel metal-oxide-semiconductor (PMOS) transistors to reduce leakage currents. Techniques that can be used to alter the amount of stressed experienced by transistors may include forming a stress-inducing layer, forming a stress liner, forming diffusion active regions using silicon germanium, silicon carbon, or standard silicon, implementing transistors in single-finger instead of multi-finger configurations, and implanting particles. Any combination of these techniques may be used to provide appropriate amounts of stress to increase the performance or decrease the total leakage current of a transistor.

摘要翻译： 提供了具有应力晶体管的集成电路。 应力晶体管可以增加晶体管阈值电压，而不需要增加沟道掺杂。 应力晶体管可能会减少总漏电流。 可能需要压缩应力N沟道金属氧化物半导体（NMOS）晶体管和拉伸应力P沟道金属氧化物半导体（PMOS）晶体管以减少漏电流。 可用于改变晶体管经受的应力的技术可包括形成应力诱导层，形成应力衬垫，使用硅锗，硅碳或标准硅形成扩散有源区，以单指代替晶体管 的多指配置和植入颗粒。 可以使用这些技术的任何组合来提供适当量的应力以增加晶体管的性能或降低总泄漏电流。

公开(公告)号：US08081502B1

公开(公告)日：2011-12-20

申请号：US12345560

申请日：2008-12-29

申请人： Irfan Rahim ,  Jun Liu ,  Andy L. Lee ,  William Bradley Vest ,  Lu Zhou ,  Qi Xiang ,  Yanzhong Yu ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar

发明人： Irfan Rahim ,  Jun Liu ,  Andy L. Lee ,  William Bradley Vest ,  Lu Zhou ,  Qi Xiang ,  Yanzhong Yu ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： An integrated circuit with memory elements is provided. The memory elements may have memory element transistors with body terminals. Body bias control circuitry may supply body bias voltages that strengthen or weaken memory element transistors to improve read and write margins. The body bias control circuitry may dynamically control body bias voltages so that time-varying body bias voltages are supplied to memory element transistors. Address transistors and latch transistors in the memory elements may be selectively strengthened and weakened. Process variations may be compensated by weakening fast transistors and strengthening slow transistors with body bias adjustments.

摘要翻译： 提供了一种具有存储元件的集成电路。 存储器元件可以具有带有主体端子的存储器元件晶体管。 体偏置控制电路可以提供加强或削弱存储元件晶体管的体偏置电压，以改善读和写余量。 体偏置控制电路可以动态地控制体偏置电压，从而将时变体偏置电压提供给存储元件晶体管。 存储元件中的地址晶体管和锁存晶体管可以被选择性地加强和削弱。 过程变化可以通过削弱快速晶体管和加强具有体偏置调整的慢晶体管来补偿。

公开(公告)号：US20100127331A1

公开(公告)日：2010-05-27

申请号：US12324789

申请日：2008-11-26

申请人： Albert Ratnakumar ,  Jun Liu ,  Jeffrey Xiaoqi Tung ,  Qi Xiang

发明人： Albert Ratnakumar ,  Jun Liu ,  Jeffrey Xiaoqi Tung ,  Qi Xiang

IPC分类号： H01L29/78 ,  G06F17/50

CPC分类号： G06F17/5063 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/78

摘要： Mixed gate metal-oxide-semiconductor transistors are provided. The transistors may have an asymmetric configuration that exhibits increased output resistance. Each transistor may be formed from a gate insulating layer formed on a semiconductor. The gate insulating layer may be a high-K material. Source and drain regions in the semiconductor may define a transistor gate length. The gate length may be larger than the minimum specified by semiconductor fabrication design rules. The transistor gate may be formed from first and second gate conductors with different work functions. The relative sizes of the first and gate conductors in a given transistor control the threshold voltage for the transistor. A computer-aided design tool may be used to receive a circuit design from a user. The tool may generate fabrication masks for the given design that include mixed gate transistors with threshold voltages optimized to meet circuit design criteria.

摘要翻译： 提供混合栅极金属氧化物半导体晶体管。 晶体管可以具有表现出增加的输出电阻的非对称配置。 每个晶体管可以由形成在半导体上的栅极绝缘层形成。 栅极绝缘层可以是高K材料。 半导体中的源极和漏极区域可以限定晶体管栅极长度。 栅极长度可以大于由半导体制造设计规则规定的最小值。 晶体管栅极可以由具有不同功函数的第一和第二栅极导体形成。 给定晶体管中的第一和栅极导体的相对尺寸控制晶体管的阈值电压。 计算机辅助设计工具可用于从用户接收电路设计。 该工具可以为给定的设计生成包括混合栅极晶体管的制造掩模，其具有优化的阈值电压以满足电路设计标准。

公开(公告)号：US20100079200A1

公开(公告)日：2010-04-01

申请号：US12241706

申请日：2008-09-30

申请人： Qi Xiang ,  Albert Ratnakumar ,  Jeffrey Xiaoqi Tung ,  Weiqi Ding

发明人： Qi Xiang ,  Albert Ratnakumar ,  Jeffrey Xiaoqi Tung ,  Weiqi Ding

IPC分类号： G05F1/10 ,  H01L21/336

CPC分类号： G05F3/205 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.

摘要翻译： 提出了使用正向偏置电路设计和改进的混合信号处理来提高模拟电路性能的方法。 定义了包括多个NMOS和PMOS晶体管的电路。 NMOS晶体管的主体端子耦合到第一电压源，并且PMOS晶体管的主体端子耦合第二电压源。 通过将第一电压源施加到每个选定的NMOS晶体管的主体端子并将第二电压源施加到每个选择的PMOS晶体管的主体端子来选择性地偏置电路中的晶体管。 在一个实施例中，第一电压源和第二电压源是可修改的，以向晶体管的主体端子提供正向和反向偏置。