公开(公告)号：US08981463B2

公开(公告)日：2015-03-17

申请号：US14105271

申请日：2013-12-13

Applicant: Micron Technology, Inc.

Inventor： Gurtej Sandhu

IPC: H01L29/66 ,  H01L27/06 ,  H01L27/102 ,  H01L27/24 ,  H01L29/88 ,  H01L27/088

CPC classification number: H01L27/0629 ,  H01L27/088 ,  H01L27/1021 ,  H01L27/24 ,  H01L29/88

Abstract: A memory array that includes access devices that are each electrically coupled to more than one memory cell. The memory cells are coupled to the access devices via diode devices. The access devices include vertical semiconductor material mesas upstanding from a semiconductor base that form a conductive channel between first and second doped regions, and also planar access devices.

Abstract translation: 一种存储器阵列，其包括各自电耦合到多于一个存储器单元的存取装置。 存储器单元通过二极管器件耦合到接入设备。 进入装置包括从形成第一和第二掺杂区域之间的导电通道的半导体基底直立的垂直半导体材料台面以及平面访问装置。

公开(公告)号：US08917542B2

公开(公告)日：2014-12-23

申请号：US13746206

申请日：2013-01-21

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej Sandhu

IPC: G11C11/02 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L43/02

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1695 ,  H01L43/02

Abstract: Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.

Abstract translation: 配置为单向编程的自旋扭矩传递磁性随机存取存储器件以及编程这种器件的方法。 这些装置包括具有两个钉扎层和其间的自由层的存储单元。 通过利用两个固定层，分别从两个固定层中的每一个自由层上的自旋转矩效应允许以单向电流编程存储器单元。

公开(公告)号：US20140299997A1

公开(公告)日：2014-10-09

申请号：US14311696

申请日：2014-06-23

Applicant: Micron Technology, Inc.

Inventor： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

Abstract: Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. Features in the selectively definable material are trimmed, and spacer material is blanket deposited over the features and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed, leaving a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.

Abstract translation: 公开了包括用于增加集成电路中的隔离特征的密度的方法。 还公开了相关联的结构。 在一些实施例中，触点是与其他结构形成的，例如可以由间距倍增形成的导电互连。 为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。 在可选择定义的材料中的特征被修整，并且间隔物材料被毯子沉积在特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。 去除可选择定义的材料，留下由间隔物材料限定的掩模。 由间隔物材料限定的图案可以转移到基底上，以形成间距接触。 在一些实施例中，上电触点可用于电接触衬底中的导电互连。

公开(公告)号：US20140241682A1

公开(公告)日：2014-08-28

申请号：US13776836

申请日：2013-02-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gurtej Sandhu ,  Roy Meade

IPC: H01L21/308 ,  G02B6/02

CPC classification number: G02B6/1225 ,  G02B6/12004 ,  G02B6/136 ,  G02B2006/12097 ,  H01L21/308

Abstract: Disclosed method and apparatus embodiments provide a photonic device with optical isolation from a supporting substrate. A generally rectangular cavity in cross section is provided below an element of the photonic device and the element may be formed from a ledge of the supporting substrate which is over the cavity.

Abstract translation: 公开的方法和设备实施例提供了一种具有与支撑衬底的光学隔离的光子器件。 在光子器件的元件的下方提供横截面的大致矩形的空腔，并且元件可以由在空腔上的支撑衬底的凸缘形成。

公开(公告)号：US08735285B2

公开(公告)日：2014-05-27

申请号：US14096052

申请日：2013-12-04

Applicant: Micron Technology, Inc.

Inventor： Gurtej Sandhu ,  Scott Sills

IPC: H01L21/44 ,  H01L21/8238

CPC classification number: H01L27/10885 ,  H01L21/28008 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/10888 ,  H01L27/10891 ,  H01L2224/06138 ,  H01L2924/12044

Abstract: An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.

Abstract translation: 集成电路和形成方法提供形成在至少一个线性延伸导线的成角度端的接触区域。 在一个实施例中，具有接触着陆焊盘的导电线通过在掩模材料中图案化线形成，切割至少一条材料线以相对于材料线的延伸方向形成一角度，从所述材料线的成角度的端面形成延伸部 掩模材料，并通过使用所述材料线和延伸作为掩模进行蚀刻来图案化下面的导体。 在另一个实施例中，至少一条导线相对于导线的延伸方向以一定角度被切割，以产生成角度的端面，并且电接触着陆垫形成为与成角度的端面接触。

公开(公告)号：US08648428B2

公开(公告)日：2014-02-11

申请号：US13835552

申请日：2013-03-15

Applicant: Micron Technology, Inc.

Inventor： Gurtej Sandhu

IPC: H01L27/088

CPC classification number: H01L27/0629 ,  H01L27/088 ,  H01L27/1021 ,  H01L27/24 ,  H01L29/88

Abstract: A memory array that includes access devices that are each electrically coupled to more than one memory cell. The memory cells are coupled to the access devices via diode devices. The access devices include vertical semiconductor material mesas upstanding from a semiconductor base that form a conductive channel between first and second doped regions, and also planar access devices.

Abstract translation: 一种存储器阵列，其包括各自电耦合到多于一个存储器单元的存取装置。 存储器单元通过二极管器件耦合到接入设备。 进入装置包括从形成第一和第二掺杂区域之间的导电通道的半导体基底直立的垂直半导体材料台面以及平面访问装置。

公开(公告)号：US20130302987A1

公开(公告)日：2013-11-14

申请号：US13941155

申请日：2013-07-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mirzafer K. Abatchev ,  Gurtej Sandhu

IPC: H01L21/308

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139

Abstract: The dimensions of mask patterns, such as pitch-multiplied spacers, are controlled by controlled growth of features in the patterns after they are formed. A pattern of mandrels is formed overlying a semiconductor substrate. Spacers are then formed on sidewalls of the mandrels by depositing a blanket layer of material over the mandrels and preferentially removing spacer material from horizontal surfaces. The mandrels are selectively removed, leaving behind a pattern of freestanding spacers. The spacers comprise a material, such as polysilicon and amorphous silicon, known to increase in size upon being oxidized. The spacers are oxidized and grown to a desired width. The spacers can then be used as a mask to pattern underlying layers and the substrate. Advantageously, because the spacers are grown by oxidation, thinner blanket layers can be deposited over the mandrels, allowing the deposition of more conformal blanket layers and widening the process window for spacer formation.

Abstract translation: 掩模图案的尺寸，例如间距倍数的间隔物，通过形成图案之后的特征的受控生长来控制。 在半导体衬底上形成心轴图案。 然后通过在心轴上沉积覆盖层材料并优先从水平表面去除间隔物材料，将垫片形成在心轴的侧壁上。 选择性地去除心轴，留下独立间隔物的图案。 间隔物包括已知在氧化时尺寸增加的材料，例如多晶硅和非晶硅。 间隔物被氧化并生长至期望的宽度。 然后可以将间隔物用作掩模以对下面的层和基底进行图案化。 有利的是，由于间隔物通过氧化生长，较薄的橡皮布层可以沉积在心轴上，允许沉积更多共形的覆盖层并加宽用于间隔物形成的工艺窗口。

公开(公告)号：US20130210230A1

公开(公告)日：2013-08-15

申请号：US13751781

申请日：2013-01-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gurtej Sandhu ,  Scott Sills

IPC: H01L21/308

CPC classification number: H01L27/10885 ,  H01L21/28008 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/10888 ,  H01L27/10891 ,  H01L2224/06138 ,  H01L2924/12044

Abstract: An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.

公开(公告)号：US20130207202A1

公开(公告)日：2013-08-15

申请号：US13835552

申请日：2013-03-15

Applicant: Micron Technology, Inc.

Inventor： Gurtej Sandhu

IPC: H01L27/088

CPC classification number: H01L27/0629 ,  H01L27/088 ,  H01L27/1021 ,  H01L27/24 ,  H01L29/88

Abstract: A memory array that includes access devices that are each electrically coupled to more than one memory cell. The memory cells are coupled to the access devices via diode devices. The access devices include vertical semiconductor material mesas upstanding from a semiconductor base that form a conductive channel between first and second doped regions, and also planar access devices.

Abstract translation: 一种存储器阵列，其包括各自电耦合到多于一个存储器单元的存取装置。 存储器单元通过二极管器件耦合到接入设备。 进入装置包括从形成第一和第二掺杂区域之间的导电通道的半导体基底直立的垂直半导体材料台面以及平面访问装置。

公开(公告)号：US20240237546A1

公开(公告)日：2024-07-11

申请号：US18615422

申请日：2024-03-25

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej Sandhu

IPC: H10N50/10 ,  G11C11/16 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  G11C11/161 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: Techniques for reducing damage in memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. In one or more embodiments, certain regions of the cell structure may be sensitive to damage. For example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. Such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. Furthermore, in some embodiments, a memory cell structure is formed and confined within a recess in dielectric material.