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    SPACER PROCESS FOR ON PITCH CONTACTS AND RELATED STRUCTURES
    3.
    发明申请
    SPACER PROCESS FOR ON PITCH CONTACTS AND RELATED STRUCTURES 审中-公开
    用于触点接触和相关结构的间隔工艺

    公开(公告)号：US20140299997A1

    公开(公告)日：2014-10-09

    申请号：US14311696

    申请日：2014-06-23

    Applicant: Micron Technology, Inc.

    Inventor： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

    IPC: H01L21/768 ,  H01L23/528

    CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

    Abstract: Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. Features in the selectively definable material are trimmed, and spacer material is blanket deposited over the features and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed, leaving a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.

    Abstract translation: 公开了包括用于增加集成电路中的隔离特征的密度的方法。 还公开了相关联的结构。 在一些实施例中，触点是与其他结构形成的，例如可以由间距倍增形成的导电互连。 为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。 在可选择定义的材料中的特征被修整，并且间隔物材料被毯子沉积在特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。 去除可选择定义的材料，留下由间隔物材料限定的掩模。 由间隔物材料限定的图案可以转移到基底上，以形成间距接触。 在一些实施例中，上电触点可用于电接触衬底中的导电互连。

    Memory Arrays and Methods of Forming Memory Cells
    4.
    发明申请
    Memory Arrays and Methods of Forming Memory Cells 有权
    记忆阵列和形成记忆单元的方法

    公开(公告)号：US20130193403A1

    公开(公告)日：2013-08-01

    申请号：US13781457

    申请日：2013-02-28

    Applicant: Micron Technology, Inc.

    Inventor： John Smythe ,  Gurtej S. Sandhu

    IPC: H01L45/00

    CPC classification number: H01L45/145 ,  H01L27/2409 ,  H01L27/2472 ,  H01L27/2481

    Abstract: Some embodiments include methods of forming memory cells utilizing various arrangements of conductive lines, electrodes and programmable material; with the programmable material containing high k dielectric material directly against multivalent metal oxide. Some embodiments include arrays of memory cells, with the memory cells including programmable material containing high k dielectric material directly against multivalent metal oxide.

    Abstract translation: 一些实施例包括利用导电线，电极和可编程材料的各种布置形成存储单元的方法; 其中可编程材料含有高k电介质材料直接抵抗多价金属氧化物。 一些实施例包括存储器单元的阵列，其中存储单元包括直接对抗多价金属氧化物的包含高k电介质材料的可编程材料。

    Memory cell arrays
    7.
    发明授权
    Memory cell arrays 有权
    存储单元阵列

    公开(公告)号：US09214627B2

    公开(公告)日：2015-12-15

    申请号：US14687738

    申请日：2015-04-15

    Applicant: Micron Technology, Inc.

    Inventor： Scott E. Sills ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  John Smythe

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1226 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/085 ,  H01L45/124 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148

    Abstract: Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first electrode. The trench-shape defines an opening. The programmable material may be configured to reversibly retain a conductive bridge. The memory cell may have an ion source material directly against the programmable material, and may have a second electrode within the opening defined by the trench-shaped programmable material. Some embodiments include arrays of memory cells. The arrays may have first electrically conductive lines, and trench-shaped programmable material structures over the first lines. The trench-shaped structures may define openings within them. Ion source material may be directly against the programmable material, and second electrically conductive lines may be over the ion source material and within the openings defined by the trench-shaped structures.

    Abstract translation: 一些实施例包括存储器单元。 存储单元可以具有第一电极和在第一电极上方的沟槽状可编程材料结构。 沟槽形状限定开口。 可编程材料可以被配置为可逆地保持导电桥。 存储单元可以具有直接抵靠可编程材料的离子源材料，并且可以在由沟槽状可编程材料限定的开口内具有第二电极。 一些实施例包括存储器单元阵列。 阵列可以具有第一导电线，以及在第一线上的沟槽状可编程材料结构。 沟槽状结构可以在其内限定开口。 离子源材料可以直接抵靠可编程材料，并且第二导电线可以在离子源材料之上并且在由沟槽状结构限定的开口内。

    Methods of forming patterns
    8.
    发明授权
    Methods of forming patterns 有权
    形成图案的方法

    公开(公告)号：US09034570B2

    公开(公告)日：2015-05-19

    申请号：US14192410

    申请日：2014-02-27

    Applicant: Micron Technology, Inc.

    Inventor： Scott E. Sills ,  Gurtej S. Sandhu ,  John Smythe ,  Ming Zhang

    IPC: G03F7/26 ,  H01L21/027 ,  G03F7/40 ,  H01L21/033 ,  G03F7/20

    CPC classification number: H01L21/0274 ,  G03F7/20 ,  G03F7/40 ,  H01L21/0337 ,  H01L21/0338

    Abstract: Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops and may have sidewalls extending downwardly from the tops. A first material may be formed along the tops and sidewalls of the features. The first material may be formed by spin-casting a conformal layer of the first material across the features, or by selective deposition along the features relative to the substrate. After the first material is formed, fill material may be provided between the features while leaving regions of the first material exposed. The exposed regions of the first material may then be selectively removed relative to both the fill material and the features to create the pattern of openings.

    Abstract translation: 一些实施例包括形成开口图案的方法。 所述方法可以包括在衬底上形成间隔的特征。 特征可以具有顶部并且可以具有从顶部向下延伸的侧壁。 第一材料可以沿着特征的顶部和侧壁形成。 第一材料可以通过将特征上的第一材料的共形层旋转浇铸而形成，或通过相对于基底的特征的选择性沉积来形成。 在形成第一材料之后，可以在特征之间提供填充材料，同时使第一材料的区域暴露。 然后可以相对于填充材料和特征来选择性地去除第一材料的暴露区域以产生开口图案。

    Memory arrays and methods of forming memory cells
    9.
    发明授权
    Memory arrays and methods of forming memory cells 有权
    存储器阵列和形成存储单元的方法

    公开(公告)号：US08530878B2

    公开(公告)日：2013-09-10

    申请号：US13781457

    申请日：2013-02-28

    Applicant: Micron Technology, Inc.

    Inventor： John Smythe ,  Gurtej S. Sandhu

    IPC: H01L47/00 ,  H01L29/06

    CPC classification number: H01L45/145 ,  H01L27/2409 ,  H01L27/2472 ,  H01L27/2481

    Abstract: Some embodiments include methods of forming memory cells utilizing various arrangements of conductive lines, electrodes and programmable material; with the programmable material containing high k dielectric material directly against multivalent metal oxide. Some embodiments include arrays of memory cells, with the memory cells including programmable material containing high k dielectric material directly against multivalent metal oxide.

    Abstract translation: 一些实施例包括利用导电线，电极和可编程材料的各种布置形成存储单元的方法; 其中可编程材料含有高k电介质材料直接抵抗多价金属氧化物。 一些实施例包括存储器单元的阵列，其中存储单元包括直接对抗多价金属氧化物的包含高k电介质材料的可编程材料。

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