公开(公告)号：US20190237559A1

公开(公告)日：2019-08-01

申请号：US15880757

申请日：2018-01-26

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Julien Frougier ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/311 ,  H01L29/423

CPC classification number: H01L29/6656 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.

公开(公告)号：US20190109177A1

公开(公告)日：2019-04-11

申请号：US15729758

申请日：2017-10-11

Applicant: International Business Machines Corporation

Inventor： Daniel Chanemougame ,  Julien Frougier ,  Nicolas J. Loubet ,  Ruilong Xie

IPC: H01L27/24 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L45/00 ,  H01L29/78

Abstract: Embodiments of the invention are directed to a method and resulting structures for a steep-switch vertical field effect transistor (SS-VFET). In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source or drain region of a substrate. A top source or drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source or drain region. A bi-stable resistive system is formed on the top metallization layer. The bi-stable resistive system includes an insulator-to-metal transition material or a threshold-switching selector. The SS-VFET provides a subthreshold switching slope of less than 60 millivolts per decade.

公开(公告)号：US10170520B1

公开(公告)日：2019-01-01

申请号：US15894128

申请日：2018-02-12

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Nicolas Loubet ,  Ruilong Xie ,  Daniel Chanemougame ,  Ali Razavieh ,  Kangguo Cheng

IPC: H01L29/02 ,  H01L27/24 ,  H01L29/06 ,  H01L23/535 ,  H01L29/78 ,  H01L45/00 ,  H01L29/66 ,  H01L21/768 ,  H01L21/28

Abstract: Fabricating a negative capacitance steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin, a source/drain, a gate, a cap disposed upon the gate, a trench contact disposed upon the source/drain, and an inter-layer dielectric. A source/drain recess is formed in the inter-layer dielectric extending to the trench contact, and a gate recess is formed in the inter-layer dielectric extending to the gate. A ferroelectric material is deposited within the gate recess, and a source/drain contact is formed within the source/drain recess. A gate contact is formed within the gate recess, and a contact recess is formed in a portion of the source/drain contact. A bi-stable resistive system (BRS) material is formed in the contact recess, and a metallization layer contact is formed upon the BRS material. A portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forms a reversible switch.

公开(公告)号：US12176345B2

公开(公告)日：2024-12-24

申请号：US17482928

申请日：2021-09-23

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Julien Frougier ,  Kangguo Cheng ,  Juntao Li ,  Chanro Park

IPC: H01L29/78 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/66

Abstract: Stacked FET devices having independent and shared gate contacts are provided. In one aspect of the invention, a stacked FET device includes: a bottom-level FET(s) having a bottom-level FET gate; a top-level FET(s) having a top-level FET gate, wherein an upper portion of the bottom-level FET gate is adjacent to the top-level FET gate; a dielectric sidewall spacer in between the upper portion of the bottom-level FET gate and the top-level FET gate; and a dielectric gate cap disposed over the bottom and top-level FET gates that includes a different dielectric material from the dielectric sidewall spacer. A device having at least one first stacked FET device and at least one second stacked FET device, and a method of forming a stacked FET device are also provided.

公开(公告)号：US20240415032A1

公开(公告)日：2024-12-12

申请号：US18332793

申请日：2023-06-12

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Ruilong Xie ,  Julien Frougier

IPC: H10N70/00 ,  H10B63/10 ,  H10N70/20

Abstract: A phase change memory cell includes a portion of a phase change material over a bi-layer heater where the bi-layer heater has a wider bottom portion on a bottom electrode and a narrower top portion of the bi-layer heater under the phase change material. A first dielectric material is inside and directly contacting the bi-layer heater. The first dielectric material surrounds an air gap in the bottom portion of the first dielectric material. The air gap is adjacent to the wider bottom portion of the bi-layer heater. The narrower top portion of the bi-layer heater is between a sidewall of the first dielectric material and a fourth dielectric material. The fourth dielectric material is above a surface of the bottom portion of the bi-layer heater and contacts a sidewall of a third dielectric material. The phase change memory cell includes a top electrode contacting the phase change material.

公开(公告)号：US20240405071A1

公开(公告)日：2024-12-05

申请号：US18328871

申请日：2023-06-05

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Julien Frougier ,  Ruilong Xie ,  Min Gyu Sung ,  Chen Zhang

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H10B12/00

Abstract: A semiconductor structure includes a nanosheet field-effect transistor having a nanosheet stack structure, and a fin field-effect transistor having a set of vertical fins. Each of the vertical fins includes an oxide semiconductor material. The nanosheet field-effect transistor and the fin field-effect transistor are in a stacked configuration.

公开(公告)号：US12150310B2

公开(公告)日：2024-11-19

申请号：US17819955

申请日：2022-08-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Julien Frougier ,  Ruilong Xie ,  Chanro Park ,  Min Gyu Sung

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H10B51/30

Abstract: Embodiments of present invention provide a ferroelectric random-access memory (FeRAM) cell. The FeRAM cell includes a vertical channel between a bottom source/drain region and a top source/drain region; a gate oxide surrounding the vertical channel; and a ferroelectric layer surrounding the gate oxide, wherein the ferroelectric layer has two or more sections of different horizontal thicknesses between the bottom source/drain region and the top source/drain region. A method of manufacturing the FeRAM cell is also provided.

公开(公告)号：US12142526B2

公开(公告)日：2024-11-12

申请号：US17656174

申请日：2022-03-23

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Chen Zhang ,  Heng Wu ,  Julien Frougier ,  Alexander Reznicek

IPC: H01L21/768 ,  H01L29/06 ,  H01L29/417

Abstract: A stacked field-effect transistors (FETs) layout and a method for fabrication are provided. The stacked FETs include a buried interconnect within the stacked devices which provides power to buried components without requiring a wired connection from a top of the stacked FET to the buried components. The buried interconnect allows for efficient scaling of the stacked devices without extraneous wiring from a top of the device to each epitaxial region/device within the overall device.

公开(公告)号：US12136655B2

公开(公告)日：2024-11-05

申请号：US17481706

申请日：2021-09-22

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Brent Anderson ,  Albert M. Young ,  Kangguo Cheng ,  Julien Frougier ,  Balasubramanian Pranatharthiharan ,  Roy R. Yu ,  Takeshi Nogami

IPC: H01L21/84 ,  H01L21/762 ,  H01L23/522 ,  H01L23/528 ,  H01L27/12 ,  H01L29/165 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a dielectric isolation layer, a plurality of gates formed above the dielectric isolation layer, a plurality of source/drain regions above the dielectric isolation layer between the plurality of gates, and at least one contact placeholder for a backside contact. The at least one contact placeholder contacts a bottom surface of a first source/drain region of the plurality of source/drain regions. The semiconductor device further includes at least one backside contact contacting a bottom surface of a second source/drain region of the plurality of source/drain regions, and a buried power rail arranged beneath, and contacting the at least one backside contact.

公开(公告)号：US20240347533A1

公开(公告)日：2024-10-17

申请号：US18300421

申请日：2023-04-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Juntao Li ,  Julien Frougier

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823475 ,  H01L21/823481

Abstract: Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a gate cut trench in a first region between a first and a second metal gate and in a second region between a first and a second source/drain region of a first and a second transistor respectively; depositing a dielectric liner in the trench lining sidewalls and a bottom of the trench; depositing a dielectric filler inside the trench above the dielectric liner, the dielectric liner thereby surrounding a bottom and sidewalls of the dielectric filler; depositing a dielectric cap covering the dielectric liner in the first region; etching the dielectric liner in the second region to create an opening exposing the source/drain region of the first transistor; and depositing a conductive material in the opening to form a source/drain contact of the first transistor. A structure formed thereby is also provided.