公开(公告)号：US20090146262A1

公开(公告)日：2009-06-11

申请号：US11952947

申请日：2007-12-07

Applicant: Huang Liu ,  Alex K.H. See ,  James Lee ,  Johnny Widodo ,  Chung Woh Lai ,  Wenzhi Gao ,  Zhao Lun ,  Shailendra Mishra ,  Liang-Choo Hsia

Inventor： Huang Liu ,  Alex K.H. See ,  James Lee ,  Johnny Widodo ,  Chung Woh Lai ,  Wenzhi Gao ,  Zhao Lun ,  Shailendra Mishra ,  Liang-Choo Hsia

IPC: H01L29/04

CPC classification number: H01L21/02639 ,  H01L21/0237 ,  H01L21/02433 ,  H01L21/02521 ,  H01L21/02609 ,  H01L21/02636 ,  H01L21/76229 ,  H01L21/823807

Abstract: An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate.

Abstract translation: 一种集成电路系统，包括：提供衬底; 在基板上沉积电介质; 在电介质上沉积隔离电介质; 通过隔离电介质和电介质形成沟槽以露出衬底; 在所述集成电路系统上沉积电介质衬垫; 处理介电衬垫以形成沟槽间隔物; 以及在所述沟槽内沉积外延生长，其包括基本上与所述衬底相同的晶体取向。

公开(公告)号：US20090132992A1

公开(公告)日：2009-05-21

申请号：US11943591

申请日：2007-11-21

Applicant: Wenzhan ZHOU ,  Liang Choo HSIA ,  Meisheng ZHOU ,  Zheng ZOU

Inventor： Wenzhan ZHOU ,  Liang Choo HSIA ,  Meisheng ZHOU ,  Zheng ZOU

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: An optical proximity correction (OPC) model incorporates inline process variation data. OPC is performed by adjusting an input mask pattern with a mask bias derived from the OPC model to correct errors in the input mask pattern.

Abstract translation: 光学邻近校正（OPC）模型包含在线过程变化数据。 通过使用从OPC模型导出的掩模偏差调整输入掩模图案来校正输入掩模图案中的错误来执行OPC。

公开(公告)号：US20090026549A1

公开(公告)日：2009-01-29

申请号：US12241073

申请日：2008-09-30

Applicant: Young Way TEH ,  Yong Meng LEE ,  Chung Woh LAI ,  Wenhe LIN ,  Khee Yong LIM ,  Wee Leng TAN ,  John SUDIJONO ,  Hui Peng KOH ,  Liang Choo HSIA

Inventor： Young Way TEH ,  Yong Meng LEE ,  Chung Woh LAI ,  Wenhe LIN ,  Khee Yong LIM ,  Wee Leng TAN ,  John SUDIJONO ,  Hui Peng KOH ,  Liang Choo HSIA

IPC: H01L29/00

CPC classification number: H01L21/823807 ,  H01L21/823864

Abstract: An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.

Abstract translation: 从NMOS晶体管的栅极去除间隔物的示例性过程。 在NMOS和PMOS晶体管和衬底上形成应力产生层。 在一个实施例中，栅极上的间隔物被去除，使得应力层更靠近器件的通道。 应力产生层优选为拉伸氮化物层。 应力产生层优选为接触蚀刻停止衬层。 在一个实施例中，在形成应力产生层之前，栅极，源极和漏极区域之前具有硅化物层。 该实施例改善了NMOS晶体管的性能。

公开(公告)号：US07326609B2

公开(公告)日：2008-02-05

申请号：US10908328

申请日：2005-05-06

Applicant: Purakh Raj Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

Inventor： Purakh Raj Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

IPC: H01L21/8238

CPC classification number: H01L21/82385 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/11 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.

Abstract translation: 用于制造半导体器件的方法和设备提供具有第一区域和第二区域的衬底。 牺牲第一栅极形成在第一区域中。 源极/漏极形成在第一区域中。 第二区域栅极电介质形成在第二区域中。 第二区域栅极形成在第二区域栅极电介质上。 在第二区域中形成第二区域源极/漏极。 在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。 牺牲的第一个门被暴露。 通过去除牺牲第一栅极形成栅极空间。 在栅极空间中形成第一区域栅极电介质。 第一区栅极形成在第一区栅极电介质上。 牺牲层被去除。

公开(公告)号：US07323408B2

公开(公告)日：2008-01-29

申请号：US11299457

申请日：2005-12-12

Applicant: Beichao Zhang ,  Wuping Liu ,  Liang-Choo Hsia

Inventor： Beichao Zhang ,  Wuping Liu ,  Liang-Choo Hsia

IPC: H01L21/4763

CPC classification number: H01L21/76843 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material. A second barrier layer is deposited, the via and trench pattern is filled with copper after which excess copper is removed by polishing the surface of the deposited layer of copper.

Abstract translation: 提供了一种用于创建铜互连的新方法。 产生铜互连的图案，半导体材料的保护层沉积在所产生的铜互连的表面上。 保护层被图案化和蚀刻，暴露铜互连图案的表面。 暴露的铜表面是Ar溅射，之后沉积第一势垒层。 去除保护材料的图案化和蚀刻层，留在覆盖铜图案的位置使第一阻挡材料的保护层互连。 沉积了一层蚀刻停止材料形式的电介质阻挡层，之后沉积了分层的蚀刻停止材料层。 通孔和沟槽图案被蚀刻成与将要建立电接触的铜图案对齐，铜图案被第一层屏障材料保护。 沉积第二阻挡层，通孔和沟槽图案填充有铜，之后通过抛光沉积的铜层的表面去除多余的铜。

公开(公告)号：US20070281410A1

公开(公告)日：2007-12-06

申请号：US11447565

申请日：2006-06-05

Applicant: Yong Meng Lee ,  Young Way Teh ,  Chung Woh Lai ,  Wenhe Lin ,  Khee Yong Lim ,  Wee Leng Tan ,  Hui Peng Koh ,  John Sudijono ,  Liang Choo Hsia

Inventor： Yong Meng Lee ,  Young Way Teh ,  Chung Woh Lai ,  Wenhe Lin ,  Khee Yong Lim ,  Wee Leng Tan ,  Hui Peng Koh ,  John Sudijono ,  Liang Choo Hsia

IPC: H01L21/8234

CPC classification number: H01L21/823864 ,  H01L21/823871 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Abstract translation: 第一示例性实施例提供了从栅极去除第一间隔物并将低k材料并入到ILD层中以提高器件性能的方法。 第二示例性实施例包括用低k间隔物硅化后替换第一间隔物。 这用于减小寄生电容。 此外，通过仅在硅化后实现低k间隔物，实施方案的低k间隔物不受多次高剂量离子注入和抗蚀剂剥离步骤的影响。 示例性实施例可以提高设备性能，例如边缘振荡器的性能。

公开(公告)号：US07271110B2

公开(公告)日：2007-09-18

申请号：US11029835

申请日：2005-01-05

Applicant: Wei Lu ,  Liang Choo Hsia

Inventor： Wei Lu ,  Liang Choo Hsia

IPC: H01L21/31

CPC classification number: H01L21/31629 ,  C23C16/345 ,  C23C16/401 ,  C23C16/505 ,  H01L21/02131 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76829

Abstract: An embodiment of the invention is a HDP CVD FSG layer and an HDP CVD SIN layer with more stability (e.g., less free F and less free H). A feature is that the FSG and SIN are formed using a HDP CVD process with a high plasma density between 1E12 and 1E15 ions/cc and more preferably between 1E14 and 1E15 ions/cc. The high bias has sufficient energy to break the F—Si bonds in the FSG. The high bias has sufficient energy to break the H—Si bonds in the silicon nitride. Whereby the FSG layer has less F and the SiN layer has less H that increases the FSG/SiN interface reliability. The embodiments can be used on smooth surfaces (non-gap fill applications).

Abstract translation: 本发明的一个实施方案是具有更稳定性（例如较少游离F和较少游离H）的HDP CVD FSG层和HDP CVD SIN层。 特征是使用具有1E12和1E15离子/ cc之间的高等离子体密度，更优选在1E14和1E15离子/ cc之间的HDP CVD工艺形成FSG和SIN。 高偏压具有足够的能量来破坏FSG中的F-Si键。 高偏压具有足够的能量来破坏氮化硅中的H-Si键。 其中FSG层具有较少的F，并且SiN层具有较小的H，从而增加了FSG / SiN界面的可靠性。 这些实施例可以用于平滑表面（非间隙填充应用）。

公开(公告)号：US07256112B2

公开(公告)日：2007-08-14

申请号：US11039429

申请日：2005-01-20

Applicant: Yung Fu Chong ,  Dong Kyun Sohn ,  Liang Choo Hsia

Inventor： Yung Fu Chong ,  Dong Kyun Sohn ,  Liang Choo Hsia

IPC: H01L21/42

CPC classification number: H01L27/105 ,  H01L21/28512 ,  H01L21/76897 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/7833

Abstract: An example method of forming a bitline contact region and bitline contact plug for a memory device using a laser irradiation activation process. An example embodiment comprises: providing a substrate having a logic region and a SONOS memory region. We form in the memory region, a memory transistor comprised of a memory gate dielectric, a memory gate electrode, memory LDD regions, memory spacers on the sidewalls of the memory gate electrode. We then perform a “memory Cell Source Line” implant to form a memory source line in the memory region adjacent to the memory gate electrode. We form silicide over the memory gate electrode and on the memory source line. We form an ILD dielectric layer over the substrate surface. We form a contact opening in the ILD dielectric layer over the memory Drain in the memory area. We etch an opening in the substrate in the drain region adjacent to the memory gate electrode. The opening exposes the memory cell first well and exposes the memory drain on the sidewall of the opening. We perform a bitline contact plug implant to from a doped contact region under the opening. We activate the doped contact region to form an activated doped contact region using a laser irradiation process. The laser irradiation process improves the electrical activation of the doped contact region without interfering with the silicide and S/D regions of the logic devices.

Abstract translation: 使用激光照射激活过程形成用于存储器件的位线接触区域和位线接触插塞的示例性方法。 示例实施例包括：提供具有逻辑区域和SONOS存储器区域的衬底。 在存储区域中形成存储器晶体管，该存储晶体管由存储栅极电介质，存储栅极电极，存储器LDD区域，存储器栅电极的侧壁上的存储器间隔构成。 然后，我们执行“存储单元源线”注入，以在与存储器栅电极相邻的存储器区域中形成存储器源极线。 我们在存储器栅电极和存储器源极线上形成硅化物。 我们在衬底表面上形成一个ILD电介质层。 我们在存储器区域中的存储器漏极上的ILD电介质层中形成接触开口。 我们蚀刻在与存储栅电极相邻的漏极区中的衬底中的开口。 开口第一次暴露存储单元并暴露开口侧壁上的存储器漏极。 我们从开口下方的掺杂接触区域执行位线接触插入注入。 我们激活掺杂接触区域，以使用激光照射工艺形成激活的掺杂接触区域。 激光照射过程改善了掺杂接触区域的电激活，而不会干扰逻辑器件的硅化物和S / D区域。

公开(公告)号：US20060083994A1

公开(公告)日：2006-04-20

申请号：US10970077

申请日：2004-10-20

Applicant: Sia Tan ,  Soon Tan ,  Qunying Lin ,  Huey Chong ,  Liang-Choo Hsia

Inventor： Sia Tan ,  Soon Tan ,  Qunying Lin ,  Huey Chong ,  Liang-Choo Hsia

IPC: G03C5/00 ,  G06F17/50 ,  G03F1/00

CPC classification number: G03F1/34 ,  G03F1/36

Abstract: A method and structure for removing side lobes is provided by positioning first and second radiation transparent regions of respective first and second phases at a first plane with the first and second phases being substantially out of phase. Further, positioning the first and the second region to cause radiation at a second plane to be neutralized in a first region, not to be neutralized in a second region, and to have a side lobe in a third region. Further, positioning a non-transparent region at the first plane to assure radiation at the second plane to be neutralized in the first region and positioning a third radiation transparent region of the first or second phase at the first plane to neutralize the side lobes in the third region at the second plane.

Abstract translation: 通过将第一和第二相的第一和第二辐射透明区域定位在第一平面上，其中第一和第二相基本上异相，来提供用于去除旁瓣的方法和结构。 此外，定位第一和第二区域以使第二平面上的辐射在第一区域中被中和，而不在第二区域中被中和，并且在第三区域中具有旁瓣。 此外，在第一平面处定位不透明区域以确保在第二平面处的辐射在第一区域中被中和，并且将第一或第二相的第三辐射透明区域定位在第一平面处以中和旁瓣 第三个地区在第二个飞机。

公开(公告)号：US20060001170A1

公开(公告)日：2006-01-05

申请号：US10882855

申请日：2004-07-01

Applicant: Fan Zhang ,  Tae Lee ,  Liang choo Hsia

Inventor： Fan Zhang ,  Tae Lee ,  Liang choo Hsia

IPC: H01L29/40 ,  H01L21/44

CPC classification number: H01L21/76882 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76886

Abstract: An interconnect structure and method thereof comprising: a interconnect and a compound cap layer. The interconnect has a compound cap layer thereover. The interconnect is preferably comprised of copper. The compound cap layer is preferably comprised of a copper-metal (Cu-Me) compound or a metal; and is more preferably comprised of a Cu—Sn compound or Ni metal. A dielectric cap layer is formed over the compound cap layer. The compound cap layer can provide a barrier capping effect to the Cu to minimize the out-diffusion of Cu and therefore improve the electro-migration performance of Cu. The compound cap layer has excellent adhesion to dielectric cap layers, especially SiN and SiC dielectric cap layers.

Abstract translation: 一种互连结构及其方法，包括：互连和复合覆盖层。 互连在其上具有复合盖层。 互连优选地由铜组成。 化合物盖层优选由铜 - 金属（Cu-Me）化合物或金属组成; 更优选由Cu-Sn化合物或Ni金属构成。 在复合盖层之上形成电介质盖层。 复合盖层可以提供Cu的阻挡封盖作用以最小化Cu的扩散，从而提高Cu的电迁移性能。 复合覆盖层对电介质盖层，特别是SiN和SiC介电盖层具有优异的粘合性。