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    Methods of Forming Resistive Memory Devices
    71.
    发明申请
    Methods of Forming Resistive Memory Devices 有权
    形成电阻式存储器件的方法

    公开(公告)号：US20100233849A1

    公开(公告)日：2010-09-16

    申请号：US12784230

    申请日：2010-05-20

    Applicant: Jang Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

    Inventor： Jang Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

    IPC: H01L21/36

    CPC classification number: H01L45/04 ,  H01L27/2418 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

    Abstract: Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.

    Abstract translation: 形成电阻性存储器件的方法包括在包括导电图案的半导体衬底上形成绝缘层，在绝缘层中形成接触孔以露出导电图案，在接触孔中形成下电极，形成可变电阻氧化物层 在下电极的接触孔中，在可变电阻氧化物层的接触孔中形成中间电极，在中间电极和绝缘层上形成缓冲氧化物层，在缓冲氧化物层上形成上电极。 还公开了相关的电阻式存储器件。

    Resistive memory devices and methods of forming resistive memory devices
    73.
    发明授权
    Resistive memory devices and methods of forming resistive memory devices 有权
    电阻式存储器件和形成电阻式存储器件的方法

    公开(公告)号：US07750336B2

    公开(公告)日：2010-07-06

    申请号：US12207889

    申请日：2008-09-10

    Applicant: Jang-Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

    Inventor： Jang-Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

    IPC: H01L47/00

    CPC classification number: H01L45/04 ,  H01L27/2418 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

    Abstract: Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.

    Abstract translation: 形成电阻性存储器件的方法包括在包括导电图案的半导体衬底上形成绝缘层，在绝缘层中形成接触孔以露出导电图案，在接触孔中形成下电极，形成可变电阻氧化物层 在下电极的接触孔中，在可变电阻氧化物层的接触孔中形成中间电极，在中间电极和绝缘层上形成缓冲氧化物层，在缓冲氧化物层上形成上电极。 还公开了相关的电阻式存储器件。

    Resistive memory devices including selected reference memory cells
    74.
    发明授权
    Resistive memory devices including selected reference memory cells 失效
    电阻式存储器件包括所选择的参考存储单元

    公开(公告)号：US07672155B2

    公开(公告)日：2010-03-02

    申请号：US12265941

    申请日：2008-11-06

    Applicant: Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    Inventor： Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    IPC: G11C11/00

    CPC classification number: G11C11/1675 ,  G11C11/1673

    Abstract: A magnetic memory cell array device can include a first current source line extending between pluralities of first and second memory cells configured for respective simultaneous programming and configured to conduct adequate programming current for writing one of the pluralities of first and second memory cells, a first current source transistor coupled to the first current source line and to a word line, a programming conductor coupled to the first current source transistor and extending across bit lines coupled to the one of the pluralities of first and second memory cells, configured to conduct the programming current across the bit lines, a second current source transistor coupled to the programming conductor and configured to switch the programming current from the programming conductor to a second current source transistor output, a second current source line extending adjacent the one of the pluralities of first and second memory cells opposite the first current source line, a first bias circuit configured to apply a first bias voltage to the first or second memory cells selected for accessed during a read operation, and a second bias circuit configured to apply a second bias voltage to the first or second memory cells unselected for access during the read operation.

    Abstract translation: 磁存储单元阵列器件可以包括在多个第一和第二存储器单元之间延伸的第一电流源线，该第一和第二存储器单元被配置用于相应的同时编程，并且被配置为进行用于写入多个第一和第二存储器单元之一的足够的编程电流，第一电流 源极晶体管，耦合到第一电流源线和字线，编程导体，其耦合到第一电流源晶体管并且延伸跨越耦合到多个第一和第二存储器单元中的一个的位线，被配置为导通编程电流 耦合到编程导体并被配置为将编程电流从编程导体切换到第二电流源晶体管输出的第二电流源晶体管，与多个第一和第二晶体管中的一个相邻延伸的第二电流源极线 与第一电流源线相对的存储单元，af 第一偏置电路，被配置为将第一偏置电压施加到在读取操作期间被选择访问的第一或第二存储器单元;以及第二偏置电路，被配置为向读取期间未选择访问的第一或第二存储器单元施加第二偏置电压 操作。

    Bipolar Resistive Memory Device Having Tunneling Layer
    78.
    发明申请
    Bipolar Resistive Memory Device Having Tunneling Layer 审中-公开
    具有隧道层的双极电阻存储器件

    公开(公告)号：US20080211036A1

    公开(公告)日：2008-09-04

    申请号：US12037400

    申请日：2008-02-26

    Applicant: Jin Shi Zhao ,  Jang-eun Lee ,  In-gyu Baek ,  Se-chung Oh ,  Kyung-tae Nam ,  Eun-kyung Yim

    Inventor： Jin Shi Zhao ,  Jang-eun Lee ,  In-gyu Baek ,  Se-chung Oh ,  Kyung-tae Nam ,  Eun-kyung Yim

    IPC: H01L29/8605 ,  H01C1/012

    CPC classification number: H01L27/115 ,  H01L27/112 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146

    Abstract: A nonvolatile memory device includes a semiconductor substrate, a first electrode on the semiconductor substrate, a resistive layer on the first electrode, a second electrode on the resistive layer and at least one tunneling layer interposed between the resistive layer and the first electrode and/or the second electrode. The resistive layer and the tunneling layer may support transition between first and second resistance states responsive to first and second voltages applied across the first and second electrodes. The first and second voltages may have opposite polarities.

    Abstract translation: 非易失性存储器件包括半导体衬底，半导体衬底上的第一电极，第一电极上的电阻层，电阻层上的第二电极和介于电阻层和第一电极之间的至少一个隧道层和/或 第二电极。 电阻层和隧道层可以响应于施加在第一和第二电极上的第一和第二电压来支持第一和第二电阻状态之间的转变。 第一和第二电压可以具有相反的极性。

    Apparatus for depositing a thin film on a substrate
    80.
    发明申请
    Apparatus for depositing a thin film on a substrate 审中-公开
    用于在基板上沉积薄膜的装置

    公开(公告)号：US20060016396A1

    公开(公告)日：2006-01-26

    申请号：US11179136

    申请日：2005-07-12

    Applicant: Bong-Jin Kuh ,  Horii Hideki ,  Soon-Oh Park ,  Jang-Eun Lee ,  Yong-Ho Ha

    Inventor： Bong-Jin Kuh ,  Horii Hideki ,  Soon-Oh Park ,  Jang-Eun Lee ,  Yong-Ho Ha

    IPC: C23C16/00

    CPC classification number: C23C14/165 ,  C23C14/046 ,  C23C14/35 ,  C23C14/50

    Abstract: An apparatus for depositing a thin film on a substrate includes a housing, a substrate support portion, a securing member, a heater, a target member and a plasma generator. The housing defines a process chamber. The substrate support portion is disposed in the process chamber to support the substrate. The securing member is adapted to non-electrically secure the substrate to the substrate support portion during performance of a process. The heater is provided to maintain the substrate supported by the substrate support portion at a process temperature. The target member faces the substrate support portion and includes materials to be deposited on the substrate. The plasma generator is adapted to excite a process gas supplied into the process chamber into a plasma state.

    Abstract translation: 用于在衬底上沉积薄膜的装置包括壳体，衬底支撑部分，固定构件，加热器，目标构件和等离子体发生器。 壳体限定了处理室。 衬底支撑部分设置在处理室中以支撑衬底。 固定构件适于在执行过程期间将基板非电气地固定到基板支撑部分。 提供加热器以将基板支撑部分支撑的基板保持在处理温度。 目标构件面向衬底支撑部分并且包括待沉积在衬底上的材料。 等离子体发生器适于将供应到处理室中的工艺气体激发成等离子体状态。

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