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    Phase-change memory devices with a self-heater structure
    2.
    发明授权
    Phase-change memory devices with a self-heater structure 有权
    具有自加热器结构的相变存储器件

    公开(公告)号：US06894305B2

    公开(公告)日：2005-05-17

    申请号：US10780073

    申请日：2004-02-17

    Applicant: Ji-hye Yi ,  Horii Hideki ,  Yong-ho Ha

    Inventor： Ji-hye Yi ,  Horii Hideki ,  Yong-ho Ha

    IPC: H01L27/10 ,  H01L45/00 ,  H01L47/00

    CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144

    Abstract: Phase change memory devices include a phase-change memory layer on a semiconductor substrate. The phase-change memory layer has a major axis that is substantially parallel to a major axis of the semiconductor substrate and has a first surface and a second surface opposite the first surface that are substantially parallel to the major axis of the phase-change memory layer. A first electrode is provided on the semiconductor substrate that is electrically connected to the first surface of the phase-change memory layer in a first contact region of the phase-change memory layer. A second electrode is provided on the semiconductor substrate that is electrically connected to the phase-change memory layer in a second contact region of the phase-change memory layer. The second contact region is space apart from the first contact region.

    Abstract translation: 相变存储器件包括半导体衬底上的相变存储层。 相变存储层具有基本上平行于半导体衬底的长轴的长轴，并且具有与第一表面相对的第一表面和与基本上平行于相变存储层的长轴的第二表面 。 第一电极设置在半导体衬底上，在相变存储层的第一接触区域中电连接到相变存储层的第一表面。 第二电极设置在半导体基板上，在相变存储层的第二接触区域中电连接到相变存储层。 第二接触区域是与第一接触区域分开的空间。

    Methods of fabricating phase changeable memory devices having reduced cell areas
    3.
    发明申请
    Methods of fabricating phase changeable memory devices having reduced cell areas 审中-公开
    制造具有减小的电池区域的相变存储器件的方法

    公开(公告)号：US20050098814A1

    公开(公告)日：2005-05-12

    申请号：US11009815

    申请日：2004-12-10

    Applicant: Horii Hideki

    Inventor： Horii Hideki

    IPC: H01L27/10 ,  G11C16/02 ,  H01L27/115 ,  H01L27/24 ,  H01L21/00

    CPC classification number: G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: Methods of fabricating phase changeable memory devices are provided. The methods include forming a first storage active region on an integrated circuit substrate having a first width. A second storage active region is formed on the integrated circuit substrate having a second width. A transistor active region is formed on the integrated circuit substrate between the first and second active regions. The first and second widths are less than a width of the transistor active region.

    Abstract translation: 提供制造相变存储器件的方法。 所述方法包括在具有第一宽度的集成电路基板上形成第一存储有源区。 在具有第二宽度的集成电路基板上形成第二存储有源区。 在第一和第二有源区之间的集成电路基板上形成晶体管有源区。 第一和第二宽度小于晶体管有源区的宽度。

    Semiconductor device and method of fabricating the same
    5.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07485559B2

    公开(公告)日：2009-02-03

    申请号：US11149153

    申请日：2005-06-10

    Applicant: Sung-Lae Cho ,  Horii Hideki

    Inventor： Sung-Lae Cho ,  Horii Hideki

    IPC: H01L21/44

    CPC classification number: H01L21/76886 ,  H01L27/115 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

    Abstract: A semiconductor device and methods thereof. The semiconductor device includes a first layer formed on a substrate, the first layer having a higher conductivity. The semiconductor device further includes a second layer formed on the first layer, the second layer including a hole exposing a portion of the first layer, the exposed portion of the first layer having a lower conductivity. The method includes forming a first layer on a substrate, the first layer having a higher conductivity, forming a second layer on the first layer, exposing a portion of the first layer by forming a hole in the second layer, performing a process on at least the exposed portion of the first layer, the process decreasing the conductivity of the exposed portion. The exposed portion including the lower conductivity or higher resistivity may block heat from conducting in the first layer.

    Abstract translation: 半导体器件及其方法。 半导体器件包括形成在衬底上的第一层，第一层具有较高的导电性。 半导体器件还包括形成在第一层上的第二层，第二层包括暴露第一层的一部分的孔，第一层的暴露部分具有较低的导电性。 该方法包括在衬底上形成第一层，第一层具有较高的导电性，在第一层上形成第二层，通过在第二层中形成孔露出第一层的一部分，至少执行一个工艺 第一层的暴露部分，该工艺降低了暴露部分的导电性。 包括较低电导率或较高电阻率的暴露部分可阻止第一层中导热的热量。

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