公开(公告)号：US20090223707A1

公开(公告)日：2009-09-10

申请号：US12041916

申请日：2008-03-04

Applicant: Sampath Komarapalayam Velayudham Karikalan ,  Rezaur Rahman Khan

Inventor： Sampath Komarapalayam Velayudham Karikalan ,  Rezaur Rahman Khan

IPC: H05K1/02 ,  H05K3/20

CPC classification number: H05K1/0224 ,  H05K1/024 ,  H05K1/0245 ,  H05K2201/0191 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09054 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/09745 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147

Abstract: Magnetic field distribution and mutual capacitance control for transmission lines are provided. A first circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, and attaching a first trace to the second surface of the dielectric material. A surface profile of the reference plane layer is modified to decrease a resistance of a return current signal path through the reference plane layer, to reduce a magnetic field coupling between the first trace and a second trace. A second circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, attaching a trace to the dielectric material, and forming a solder mask layer on the dielectric material layer over the trace. An effective dielectric constant of the solder mask layer is modified to reduce or increase a mutual capacitance between the first trace and a second trace on the dielectric material.

Abstract translation: 提供传输线的磁场分布和互电容控制。 通过将参考平面层附着到介电材料层并且将第一迹线附接到电介质材料的第二表面来制造第一电路板。 修改参考平面层的表面轮廓以减小通过参考平面层的返回电流信号路径的电阻，以减小第一迹线和第二迹线之间的磁场耦合。 通过将参考平面层附着到电介质材料层，将迹线附着到电介质材料上，以及在迹线上的介电材料层上形成焊料掩模层来制造第二电路板。 修改焊接掩模层的有效介电常数以减小或增加介电材料上的第一迹线和第二迹线之间的互电容。

公开(公告)号：US20090166860A1

公开(公告)日：2009-07-02

申请号：US12125155

申请日：2008-05-22

Applicant: Sang Gon Lee ,  Dae Sung Kim ,  Woo Hyuck Chang

Inventor： Sang Gon Lee ,  Dae Sung Kim ,  Woo Hyuck Chang

IPC: H01L23/488 ,  B32B7/02 ,  B32B15/00 ,  B32B3/10

CPC classification number: H05K3/388 ,  H01L2224/16225 ,  H01L2924/12044 ,  H05K1/028 ,  H05K1/147 ,  H05K1/189 ,  H05K3/243 ,  H05K2201/0191 ,  H05K2201/0338 ,  H05K2201/10128 ,  H05K2201/10681 ,  Y10T428/12389 ,  Y10T428/24917 ,  Y10T428/2495 ,  H01L2924/00

Abstract: A flexible film is provided. The flexible film includes a dielectric film; and a metal layer disposed on the dielectric film, wherein the ratio of the thickness of the metal layer to the thickness of the dielectric film is about 1:3 to 1:10. Therefore, it is possible to improve the peel strength, dimension stability, and tensile strength of a flexible film by limiting the ratio of the thicknesses of a dielectric film and a metal layer of the flexible film.

Abstract translation: 提供柔性膜。 柔性膜包括电介质膜; 以及设置在所述电介质膜上的金属层，其中所述金属层的厚度与所述电介质膜的厚度的比率为约1:3至1:10。 因此，可以通过限制柔性膜的电介质膜和金属层的厚度的比例来提高柔性膜的剥离强度，尺寸稳定性和拉伸强度。

公开(公告)号：US20090151988A1

公开(公告)日：2009-06-18

申请号：US12213570

申请日：2008-06-20

Applicant: Kyung Ho Lee ,  Se Min Oh ,  Chang Hwan Choi ,  Choon Keun Lee ,  Jeong Yeol Moon ,  Jong Rip Kim

Inventor： Kyung Ho Lee ,  Se Min Oh ,  Chang Hwan Choi ,  Choon Keun Lee ,  Jeong Yeol Moon ,  Jong Rip Kim

IPC: H05K1/02 ,  H05K3/22

CPC classification number: H05K1/028 ,  H05K1/0218 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/0715 ,  H05K2201/09736 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126

Abstract: An FPCB and a method of manufacturing the same, in which an electrical signal-conductive portion of the FPCB is subjected to little stress so as not to be broken by fatigue in spite of repeated bending of the FPCB, thereby increasing the lifetime of the FPCB.

Abstract translation: FPCB及其制造方法，其中FPCB的电信号传导部分经受很小的应力，以便尽管FPCB的反复弯曲而不会被疲劳破坏，从而增加FPCB的寿命 。

公开(公告)号：US20090091019A1

公开(公告)日：2009-04-09

申请号：US12335372

申请日：2008-12-15

Applicant: Joseph Charles Fjelstad

Inventor： Joseph Charles Fjelstad

IPC: H01L23/48 ,  H01L23/58

CPC classification number: G11C5/04 ,  B82Y10/00 ,  G01R31/2822 ,  G11C5/063 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6627 ,  H01L2223/6633 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49433 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/1903 ,  H01L2924/19039 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01P3/08 ,  H01P5/028 ,  H05K1/024 ,  H05K1/0243 ,  H05K2201/0191 ,  H05K2201/09154 ,  H05K2201/09727 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Disclosed are IC package structures having stair stepped layers and which have no plated vias. Such structures can be fabricated either as discrete packages or as strips such as might be beneficial in for use with memory devices wherein critical or high speed signals can be routed along the length of the multi-chip strip package without having to have the signals ascend and descend from the interconnection substrate on which the assembly is mounted to the IC package termination and back as the signal transmits between devices.

Abstract translation: 公开了具有楼梯阶层并且没有电镀通孔的IC封装结构。 这样的结构可以被制造成分立的封装或者条带，例如可能有利于与存储器件一起使用，其中关键或高速信号可以沿着多芯片条封装的长度布线，而不必使信号上升， 随着信号在设备之间传输，从其上安装组件的互连基板下降到IC封装端接和返回。

公开(公告)号：US07500792B2

公开(公告)日：2009-03-10

申请号：US11142421

申请日：2005-05-31

Applicant: Daniel Supper

Inventor： Daniel Supper

IPC: G02B6/42

CPC classification number: H05K1/0271 ,  G02B6/4201 ,  G02B6/421 ,  G02B6/4281 ,  G02B6/4283 ,  H05K1/182 ,  H05K1/189 ,  H05K2201/0191 ,  H05K2201/09036 ,  H05K2201/10121

Abstract: An optoelectronic transmitting and/or receiving arrangement having: at least one optoelectronic component; an electrical printed circuit board having electrical contact areas for electrical contact-connection of the optoelectronic component; and a coupling arrangement for coupling light between the optoelectronic component and an optical waveguide to be coupled. In this case, the optoelectronic component is arranged directly on the printed circuit board and the printed circuit board is configured in such a way that a movable mounting of the optoelectronic component relative to the printed circuit board is present. A strain relief for the optoelectronic component is thereby provided as a result.

Abstract translation: 一种光电发射和/或接收装置，具有：至少一个光电子部件; 具有用于光电子部件的电接触连接的电接触区域的电印刷电路板; 以及用于在光电子部件和要耦合的光波导之间耦合光的耦合装置。 在这种情况下，光电子部件直接布置在印刷电路板上，并且印刷电路板被配置为使得光电子部件相对于印刷电路板的可移动安装存在。 因此，由此提供了光电子部件的应变消除。

公开(公告)号：US20090032285A1

公开(公告)日：2009-02-05

申请号：US11814698

申请日：2005-01-27

Applicant: Yoji Ueda ,  Susumu Matsuoka ,  Rikiya Okimoto ,  Shozo Ochi ,  Satoru Tomekawa

Inventor： Yoji Ueda ,  Susumu Matsuoka ,  Rikiya Okimoto ,  Shozo Ochi ,  Satoru Tomekawa

IPC: H05K3/46 ,  H05K1/14 ,  H05K1/00

CPC classification number: H05K1/024 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4652 ,  H05K2201/0191 ,  H05K2201/0355 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/10378 ,  H05K2203/061 ,  H05K2203/1461 ,  Y10T428/24843

Abstract: A method of manufacturing a multilayered circuit board includes the steps of: manufacturing a laminated body by laminating a prepreg of a predetermined thickness on at least one surface of a double-sided circuit board having a grounding link and a signal wiring patterned on both surfaces thereof; and applying heat and pressure to the laminated body and completing a layered structure in which the signal wiring is laid inside the prepreg at a boundary between the double-sided circuit board and the prepreg, wherein prepreg sheets of a predetermined thickness are used in a completed layered structure so that a thickness of a prepreg of the double-sided circuit board is smaller than a distance between a surface of the prepreg on a side not opposed to the double-sided circuit board and the signal wiring laid inside the prepreg.

Abstract translation: 一种制造多层电路板的方法包括以下步骤：通过在具有接地链路的双面电路板和在其两个表面上图案化的信号布线的至少一个表面层压预定厚度的预浸料来制造层压体 ; 并且对层压体施加热和压力，并且完成在双面电路板和预浸料坯之间的边界处将信号布线放置在预浸料坯内部的层状结构，其中预定厚度的预浸料片材用于完成 使得双面电路板的预浸料坯的厚度小于与双面电路板不相对的一侧上的预浸料坯的表面与布置在预浸料坯内部的信号线之间的距离。

公开(公告)号：US20090027137A1

公开(公告)日：2009-01-29

申请号：US12128620

申请日：2008-05-29

Applicant: Joseph C. Fjelstad ,  Kevin P. Grundy ,  Para K. Segaram ,  Gary Yasumura

Inventor： Joseph C. Fjelstad ,  Kevin P. Grundy ,  Para K. Segaram ,  Gary Yasumura

IPC: H03H7/38

CPC classification number: H05K1/0243 ,  G01R31/2822 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6627 ,  H01L2223/6633 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/1903 ,  H01L2924/19039 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01P3/08 ,  H01P5/028 ,  H05K1/024 ,  H05K2201/0191 ,  H05K2201/09154 ,  H05K2201/09727 ,  Y10S438/981 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Disclosed are tapered dielectric and conductor structures which provide controlled impedance interconnection while signal conductor lines transition from finer pitches to coarser pitches thereby obviating electrical discontinuities generally associated with changes of circuit contact pitch. Also disclosed are methods for the construction of the devices and applications therefore.

Abstract translation: 公开了锥形电介质和导体结构，其提供受控的阻抗互连，同时信号导体线从更细的间距转换到较粗的间距，从而消除通常与电路接触间距的变化相关的电中断。 还公开了用于构造装置和应用的方法。

公开(公告)号：US07453143B2

公开(公告)日：2008-11-18

申请号：US10793363

申请日：2004-03-04

Applicant: Achyut Dutta

Inventor： Achyut Dutta

IPC: H01Q3/46

CPC classification number: H01L23/66 ,  H01L23/5383 ,  H01L25/0655 ,  H01L2223/6627 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/1903 ,  H01L2924/19032 ,  H01L2924/19033 ,  H01L2924/3011 ,  H01P1/2005 ,  H01P3/08 ,  H05K1/0224 ,  H05K1/0236 ,  H05K1/024 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/0313 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/09681 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A high-speed electrical interconnection system is provided. The interconnection system comprises one or more electrical signal lines, or differential pairs of signal lines, and an in homogeneous dielectric system. The dielectric system further comprises a homogeneous dielectric layer interposed between the electrical signal lines, and an electrical conducting plane including a periodic array etched in the conducting material of the conducting plane. The inhomogeneous dielectric system exhibits a lower effective dielectric constant as compared to the dielectric constant of the homogeneous dielectric layer, resulting in lower microwave loss, reduced signal propagation delay, reduced signal skew and increased signal bandwidth. The interconnection system may be implemented for connecting one or more high speed electronic elements on-chip, off-chip, chip-chip connection on multilayer printed circuit boards, high speed die-package, high speed connectors and high speed electric cables.

Abstract translation: 提供了一种高速电气互连系统。 互连系统包括一个或多个电信号线或信号线的差分对，以及均匀的电介质系统。 电介质系统还包括介于电信号线之间的均匀介电层，以及包括蚀刻在导电平面的导电材料中的周期性阵列的导电平面。 与均匀介电层的介电常数相比，非均匀介电系统具有较低的有效介电常数，导致较低的微波损耗，降低的信号传播延迟，降低的信号偏移和增加的信号带宽。 互连系统可以实现用于连接多层印刷电路板上的一个或多个高速电子元件片上芯片，芯片芯片连接，高速模组封装，高速连接器和高速电缆。

公开(公告)号：US20080257472A1

公开(公告)日：2008-10-23

申请号：US11955809

申请日：2007-12-13

Applicant: Hiroshi Asano

Inventor： Hiroshi Asano

IPC: H01B13/32

CPC classification number: C04B37/006 ,  B32B18/00 ,  B32B2311/08 ,  B32B2311/09 ,  C04B35/472 ,  C04B35/491 ,  C04B35/493 ,  C04B37/021 ,  C04B41/80 ,  C04B2235/3227 ,  C04B2235/3251 ,  C04B2235/3267 ,  C04B2235/3272 ,  C04B2235/656 ,  C04B2237/346 ,  C04B2237/348 ,  C04B2237/40 ,  C04B2237/408 ,  C04B2237/704 ,  C04B2237/706 ,  H05K1/0306 ,  H05K3/0011 ,  H05K3/0097 ,  H05K3/1291 ,  H05K2201/0191 ,  H05K2203/1126 ,  H05K2203/1536 ,  Y10T156/1105 ,  Y10T156/1111

Abstract: In a method for manufacturing ceramic plates, a Pd paste which does not diffuse into ceramic is formed in a metal paste forming step; metal films each having a thickness such that ceramic layers to be formed after firing are not connected to each other in the lamination direction are formed on surfaces of ceramic green sheets using the Pd paste in a metal film forming step; following a laminate forming step, a firing treatment at a firing temperature, which is a high temperature at which no glass component remains on surfaces of the ceramic layers after the firing and which is equal to or lower than a decomposition temperature of a ceramic material forming the ceramic layers, is performed for a laminate in a firing step; oxygen present at the interfaces between the ceramic layers and the metal layers is removed by immersing a sintered body in n-butyl alcohol in a separation step so as to separate the ceramic layers and the metal layers. Accordingly, ceramic plates having a very small thickness can be manufactured without causing any damage thereto and with high efficiency and can be easily applied to laminate type electronic components.

Abstract translation: 在陶瓷板的制造方法中，在金属糊剂形成工序中形成不扩散到陶瓷中的Pd糊料， 在金属膜形成工序中，使用Pd膏在陶瓷生片的表面上形成均匀的厚度的烧成后的陶瓷层在层叠方向上不连接的厚度的金属膜， 在层叠形成工序之后，在烧成温度下进行烧成温度的烧成处理，该烧成温度是烧成后的陶瓷层的表面上不残留有玻璃成分的高温，其等于或低于形成陶瓷材料的分解温度 在烧成工序中对层叠体进行陶瓷层的制造; 通过在分离步骤中将烧结体浸渍在正丁醇中以分离陶瓷层和金属层来除去存在于陶瓷层和金属层之间的界面处的氧。 因此，可以制造具有非常小的厚度的陶瓷板，而不会对其造成任何损害并且高效率并且可以容易地应用于层压型电子部件。

公开(公告)号：US20080217049A1

公开(公告)日：2008-09-11

申请号：US12045660

申请日：2008-03-10

Applicant: George Dudnikov

Inventor： George Dudnikov

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H01G4/06 ,  H01G4/30 ,  H01G4/306 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/18 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/0355 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09663 ,  H05K2203/162 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49036 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.