公开(公告)号：US20150255334A1

公开(公告)日：2015-09-10

申请号：US14720264

申请日：2015-05-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Ching-Fu Yeh ,  Tz-Jun Kuo ,  Hsiang-Huan Lee ,  Ming-Han Lee

IPC分类号： H01L21/768

CPC分类号： H01L21/76873 ,  C25D3/38 ,  C25D7/123 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/44 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879

摘要： Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.

摘要翻译： 这里提出的是一种电镀方法，包括提供一个具有形成在一个迹线上的电介质层的衬底，以及形成延伸穿过该电介质层的通孔/沟槽开口，该通孔/沟槽开口暴露该迹线的表面。 该方法还包括在通孔/沟槽开口中形成种子层并与迹线接触并在种子层上形成保护层。 去除保护层，并通过在通孔/沟槽开口中施加电镀溶液，在单个电镀工艺步骤中在种子层上沉积导电层。

公开(公告)号：US11967552B2

公开(公告)日：2024-04-23

申请号：US17402942

申请日：2021-08-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/522 ,  H01L21/027 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76892 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53252

摘要： A method of fabricating a semiconductor interconnect structure includes forming a via in a dielectric layer, depositing a ruthenium-containing conductive layer over a top surface of the via and a top surface of the dielectric layer, and patterning the ruthenium-containing conductive layer to form a conductive line over the top surface of the via, where a thickness of the conductive line is less than a thickness of the via.

公开(公告)号：US11594483B2

公开(公告)日：2023-02-28

申请号：US16714444

申请日：2019-12-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

摘要： A semiconductor structure includes a semiconductor substrate, a via, a first dielectric layer, a first graphene layer, a metal line, and a second graphene layer. The via is over the semiconductor substrate. The first dielectric layer laterally surrounds the via. The first graphene layer extends along a top surface of the via. The metal line is over the via and is in contact with the first graphene layer. The second graphene layer peripherally encloses the metal line and the first graphene layer.

公开(公告)号：US20220367346A1

公开(公告)日：2022-11-17

申请号：US17873590

申请日：2022-07-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768

摘要： The present disclosure provides a semiconductor device that includes a substrate, a first dielectric layer over the substrate, and an interconnect layer over the first dielectric layer. The interconnect layer includes a plurality of metal lines and a second dielectric layer filling space between the plurality of metal lines. The plurality of metal lines includes a first metal line having a first bulk metal layer of a noble metal and a second metal line having a second bulk metal layer of a non-noble metal.

公开(公告)号：US20220367244A1

公开(公告)日：2022-11-17

申请号：US17869702

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/528

摘要： A semiconductor device is provided. The semiconductor device includes a dielectric layer over a substrate and a contact structure embedded in the dielectric layer. The contact structure includes a diffusion barrier contacting the dielectric layer, the diffusion barrier including a titanium (Ti)-containing alloy. The contact structure further includes a liner on the diffusion barrier, the liner including a noble metal. The contact structure further includes a conductive plug on the liner.

公开(公告)号：US20220359413A1

公开(公告)日：2022-11-10

申请号：US17308361

申请日：2021-05-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Meng-Pei Lu ,  Chin-Lung Chung ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3105

摘要： The present disclosure relates to an integrated chip. The integrated chip includes a substrate. A first conductive feature is over the substrate. A second conductive feature is over the substrate and is adjacent to the first conductive feature. The first and second conductive features are separated by a cavity. A dielectric liner extends from the first conductive feature to the second conductive feature along a bottom of the cavity and further extends along opposing sidewalls of the first and second conductive features. A dielectric cap covers and seals the cavity. The dielectric cap has a top surface that is approximately planar with top surfaces of the first and second conductive features. The first conductive feature and the second conductive feature comprise graphene intercalated with one or more metals.

公开(公告)号：US11309241B2

公开(公告)日：2022-04-19

申请号：US16908942

申请日：2020-06-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Hsin-Yen Huang ,  Ming-Han Lee ,  Shau-Lin Shue ,  Yu-Chen Chan ,  Meng-Pei Lu

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a lower dielectric arranged over a substrate. An interconnect wire is arranged over the dielectric layer, and a first interconnect dielectric layer is arranged outer sidewalls of the interconnect wire. A protection liner that includes graphene is arranged directly on the outer sidewalls of the interconnect wire and on a top surface of the interconnect wire. The integrated chip further includes a first etch stop layer arranged directly on upper surfaces of the first interconnect dielectric layer, and a second interconnect dielectric layer arranged over the first interconnect dielectric layer and the interconnect wire. Further, an interconnect via extends through the second interconnect dielectric layer, is arranged directly over the protection liner, and is electrically coupled to the interconnect wire.

公开(公告)号：US11296026B2

公开(公告)日：2022-04-05

申请号：US17004354

申请日：2020-08-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522

摘要： A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, and a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate. In a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is covered by a first two-dimensional material layer.

公开(公告)号：US20220020694A1

公开(公告)日：2022-01-20

申请号：US17391216

申请日：2021-08-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Yu-Chen Chan ,  Ming-Han Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/522

摘要： A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature.

公开(公告)号：US20210265172A1

公开(公告)日：2021-08-26

申请号：US16801526

申请日：2020-02-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3213 ,  C09G1/02 ,  H01L21/67

摘要： The present disclosure provides a method for fabricating a semiconductor structure that includes a first dielectric layer over a semiconductor substrate, and a first cap layer over the first dielectric layer. The method includes forming a first metal feature in the first dielectric layer; performing a first CMP process on the first metal feature using a first rotation rate; and performing a second CMP process on the first metal feature using a second rotation rate slower than the first rotation rate. The second CMP process may be time-based. The second CMP process may stop on the first cap layer. After performing the second CMP process, the method includes removing the first cap layer. The first CMP process may have a first polishing rate to the first metal feature. The second CMP process may have a second polishing rate to the first metal feature lower than the first polishing rate.