- 专利标题： Graphene-Assisted Low-Resistance Interconnect Structures and Methods of Formation Thereof
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申请号： US17391216申请日： 2021-08-02
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公开(公告)号： US20220020694A1公开(公告)日： 2022-01-20
- 发明人: Shin-Yi Yang , Yu-Chen Chan , Ming-Han Lee , Hai-Ching Chen , Shau-Lin Shue
- 申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 主分类号： H01L23/532
- IPC分类号： H01L23/532 ; H01L21/768 ; H01L23/522
摘要：
A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature.
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